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AN2316 Datasheet(PDF) 17 Page - STMicroelectronics |
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AN2316 Datasheet(HTML) 17 Page - STMicroelectronics |
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17 / 24 page ![]() AN2316 - Application Note ST7FLITE05 Software Description 17/24 4.1 Peripheral Initialization The peripherals are initialized. After initialization, the firmware waits 255ms for the hardware to be start up. The potentiometer is read, and the digital values are used to compute those to be loaded into the successive DCR registers. Initialization activities include the following: 4.1.1 Auto-reload Timer (AT) Configuration The 12-bit AT is configured in PWM mode so that the ATR registers contain the auto-reload value used to set the PWM frequency. 4.1.2 PWM Duty Cycle, Overflow and Compare Interrupts The PWM frequency and the DCR registers contain the value which sets the PWM duty cycle. Furthermore, the PWM output on the ATPW0 pin is enabled by setting the OE0 Bit in the PWMCR register, and both, the overflow and compare interrupts have been enabled. Note: In order to guarantee the proper operation of the overall system, using very high and very low duty cycle values are discouraged. If the duty cycle exceeds a higher threshold, the PWM must be switched off and the microcontroller pin must be kept continuously in logic high state. The PWM output is enabled again only if the user turns the potentiometer so the corresponding duty cycle is below the higher threshold minus hysteresis (see Figure 9 on page 16). If the duty cycle goes below a lower threshold, the PWM must be switched off and the microcontroller pin must kept continuously in logic low state. The PWM output is enabled again only if the duty cycle related to the potentiometer position goes above the lower threshold plus hysteresis (see Figure 9). 4.1.3 ST7LITE Timer The 8-bit LITE Timer is configured so that an overflow event (and the related interrupt) occurs every millisecond. This allows users to have a time base at their disposal to implement, for example, the soft variation of the PWM duty cycle. 4.1.4 Channel 0 A/D Conversion The 8-bit A/D conversion of Channel 0 is enabled at the fcpu/2 frequency. |
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