AN2476 datasheet(19/49 Pages) STMICROELECTRONICS

19 / 49 page

AN2476

Power supply and clocks

19/49

This procedure is performed by the function of the library described in the Section 2.6:

MRCC_EnterSTOPMode on page 30

LP mode control parameters

To further reduce power consumption in STOP mode, additional parts of the MCU can be

disabled when entering STOP Mode. This can be configured by programming the

LP_PARAM[15:13] bits in the MRCC_PWRCTRL register:

●

OSC4M and PLL OFF (LP_PARAM15): This removes the power consumption of the

PLL and the OSC4M oscillator, however the clock configuration returns to its reset

state. So when resuming from Stop mode after a wake-up event, it is necessary to

manage the start-up time for oscillator stabilization and to re-enable the PLL.

●

FLASH OFF (LP_PARAM14): This saves the static power consumption of the Flash,

but some latency for Flash start-up is incurred when waking up from STOP mode.

●

MVREG OFF (LP_PARAM13): When this parameter is set, the LPVREG (Low Power

Voltage Regulator) powers the whole circuit, saving the static consumption of the

MVREG (Main Voltage Regulator). In addition, the OSC4M oscillator, PLL and Flash

are also switched off (all three LP_PARAM bits 13, 14 and 14 are set) because the Low

power regulator does not have enough power to drive them. When resuming from Stop

mode after a wake-up event, start-up latency is incurred.

Note:

When using the LP_PARAM15 bit to switch off OSC4M in STOP mode, it is recommended

to clear the NCKDF bit just before entering STOP mode. Otherwise, if NCKDF=1 when

entering STOP mode, OSC4M will not be disabled and will continue to use power.

If OSC4M is not used as the system clock source, it is strongly recommended to switch it off

by setting the OSC4MOFF bin STOP mode even if LP_PARAM 15 is set and NCKDF is

cleared as recommended in note 1 above.

AN2476 Datasheet(PDF) 19 Page - STMicroelectronics