AN2857

Clock management

Doc ID 15241 Rev 3

11/31

The default clock after reset is HSI/8. The user can then switch the clock to different

frequencies and sources by:

●

Choosing another prescaler (/1, /2, /4 or /8) for an internal RC 16 MHz (HSI) clock

through the HSIDIV[1:0] bits in the CLK_CKDIVR register.

●

Changing the clock master (to HSE or LSI ). Refer to the STM8S and STM8A reference

manual for more details about the clock switching mechanism.

Before switching off a previous clock source when using automatic switching mode, the user

must ensure that the core is no longer running on the current clock. This means that the

previous clock must be turned off after the SWIF flag has been set. If the user tries to switch

off the clock and the SWIF flag has not been set by hardware, the current clock is not

switched off as the microcontroller is still running on it.

Such clock switching can be combined with wait mode (for example, if the HSE crystal is the

new clock) as clock switch execution interrupt can wake up the MCU from wait mode. This

allows the MCU wakeup to be synchronized with the new clock availability.

The clock switching feature can also be used at the beginning and end of a regular or

interrupt routine to speed it up (for instance, if the clock master is LSI RC, but, some parts of

the code have to be executed quickly with HSI RC).

Note:

When the device is running on an external clock with a frequency above 16 MHz, the wait

state bit in the option bytes has to be set. This adds a wait state to the Flash memory

access.

3.2

Clock configuration and power management

In addition to the flexibility of the clock sources, different complementary clock

configurations and features are available to optimize power consumption of the device:

●

PCG: Each peripheral clock can be switched off through the CLK_PCKENRx registers.

●

CPU clock divider from 1 to 128 (CPUDIV[0:2] bits from the CLK_CKDIVR register):

The CPU frequency can be decreased and not the frequency of the peripherals.

Table 2.

Clock selection table

Register value

Clock master source

(CLK_CMSR)

Next clock master

(CLK_SWR)

E1h

HSI

HSI

D2h

LSI

LSI

B4h

HSE

HSE

Other

Reset

Current clock master kept