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LT1933

1933fe

APPLICATIONS INFORMATION

PCB Layout

For proper operation and minimum EMI, care must be

taken during printed circuit board layout. Figure 8 shows

the recommended component placement with trace,

ground plane and via locations. Note that large, switched

currents ﬂow in the LT1933’s VIN and SW pins, the catch

diode (D1) and the input capacitor (C2). The loop formed

by these components should be as small as possible and

tied to system ground in only one place. These components,

along with the inductor and output capacitor, should be

placed on the same side of the circuit board, and their

connections should be made on that layer. Place a local,

unbroken ground plane below these components, and tie

this ground plane to system ground at one location, ideally

at the ground terminal of the output capacitor C1. The SW

and BOOST nodes should be as small as possible. Finally,

keep the FB node small so that the ground pin and ground

traces will shield it from the SW and BOOST nodes. Include

two vias near the GND pin of the LT1933 to help remove

heat from the LT1933 to the ground plane.

Figure 8a shows the layout for the DFN package. Vias

near and under the exposed die attach paddle minimize

the thermal resistance of the LT1933.

Figure 8. A Good PCB Layout Ensures Proper, Low EMI Operation

GND

VOUT

VIAS

VIN

1933 F08a

SHUTDOWN

VIAS

OUTLINE OF LOCAL GROUND PLANE

VIN

VOUT

1933 F08b

SYSTEM

GROUND

(8a)

DFN Package

(8b)

SOT-23 Package

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