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PM0056 Datasheet(PDF) 69 Page - STMicroelectronics |
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PM0056 Datasheet(HTML) 69 Page - STMicroelectronics |
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69 / 156 page  DocID15491 Rev 5 69/156 PM0056 The Cortex-M3 instruction set Operation PUSH stores registers on the stack in order of decreasing register numbers, with the highest numbered register using the highest memory address and the lowest numbered register using the lowest memory address. POP loads registers from the stack in order of increasing register numbers, with the lowest numbered register using the lowest memory address and the highest numbered register using the highest memory address. See LDM and STM on page 67 for more information. Restrictions In these instructions: • ‘reglist’ must not contain SP • For the PUSH instruction, reglist must not contain PC • For the POP instruction, reglist must not contain PC if it contains LR When PC is in reglist in a POP instruction: • bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfword-aligned address. • If the instruction is conditional, it must be the last instruction in the IT block. Condition flags These instructions do not change the flags. Examples PUSH{R0,R4-R7} PUSH{R2,LR} POP{R0,R10,PC} |
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