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PM0056 Datasheet(PDF) 47 Page - STMicroelectronics |
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PM0056 Datasheet(HTML) 47 Page - STMicroelectronics |
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47 / 156 page  DocID15491 Rev 5 47/156 PM0056 The Cortex-M3 instruction set LDREXB Rt, [Rn] Load register exclusive with byte — 3.4.8 on page 70 LDREXH Rt, [Rn] Load register exclusive with halfword — 3.4.8 on page 70 LDRH, LDRHT Rt, [Rn, #offset] Load register with halfword — 3.4 on page 60 LDRSB, LDRSBT Rt, [Rn, #offset] Load register with signed byte — 3.4 on page 60 LDRSH, LDRSHT Rt, [Rn, #offset] Load register with signed halfword — 3.4 on page 60 LDRT Rt, [Rn, #offset] Load register with word — 3.4 on page 60 LSL, LSLS Rd, Rm, <Rs|#n> Logical shift left N,Z,C 3.5.3 on page 76 LSR, LSRS Rd, Rm, <Rs|#n> Logical shift right N,Z,C 3.5.3 on page 76 MLA Rd, Rn, Rm, Ra Multiply with accumulate, 32-bit result — 3.6.1 on page 83 MLS Rd, Rn, Rm, Ra Multiply and subtract, 32-bit result — 3.6.1 on page 83 MOV, MOVS Rd, Op2 Move N,Z,C 3.5.6 on page 79 MOVT Rd, #imm16 Move top — 3.5.7 on page 80 MOVW, MOV Rd, #imm16 Move 16-bit constant N,Z,C 3.5.6 on page 79 MRS Rd, spec_reg Move from special register to general register — 3.9.6 on page 100 MSR spec_reg, Rm Move from general register to special register N,Z,C,V 3.9.7 on page 101 MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result N,Z 3.6.1 on page 83 MVN, MVNS Rd, Op2 Move NOT N,Z,C 3.5.6 on page 79 NOP — No operation — 3.9.8 on page 102 ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N,Z,C 3.5.2 on page 75 ORR, ORRS {Rd,} Rn, Op2 Logical OR N,Z,C 3.5.2 on page 75 POP reglist Pop registers from stack — 3.4.7 on page 68 Table 20. Cortex-M3 instructions (continued) Mnemonic Operands Brief description Flags Section |
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