PM0056 datasheet(32/156 Pages) STMICROELECTRONICS

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The Cortex-M3 processor

PM0056

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Software can use the synchronization primitives to implement a semaphores as follows:

Use a Load-Exclusive instruction to read from the semaphore address to check

whether the semaphore is free.

If the semaphore is free, use a Store-Exclusive to write the claim value to the

semaphore address.

If the returned status bit from step 2 indicates that the Store-Exclusive succeeded then

the software has claimed the semaphore. However, if the Store-Exclusive failed,

another process might have claimed the semaphore after the software performed step

The Cortex-M3 includes an exclusive access monitor, that tags the fact that the processor

has executed a Load-Exclusive instruction.

The processor removes its exclusive access tag if:

•

It executes a CLREX instruction

•

It executes a Store-Exclusive instruction, regardless of whether the write succeeds.

•

An exception occurs. This means the processor can resolve semaphore conflicts

between different threads.

For more information about the synchronization primitive instructions, see LDREX and

STREX on page 70 and CLREX on page 71.

2.2.8

Programming hints for the synchronization primitives

ANSI C cannot directly generate the exclusive access instructions. Some C compilers

provide intrinsic functions for generation of these instructions:

The actual exclusive access instruction generated depends on the data type of the pointer

passed to the intrinsic function. For example, the following C code generates the require

LDREXB operation:

__ldrex((volatile char *) 0xFF);

Table 15. C compiler intrinsic functions for exclusive access instructions

Instruction

Intrinsic function

LDREX, LDREXH, or LDREXB unsigned int __ldrex(volatile void *ptr)

STREX, STREXH, or STREXB int __strex(unsigned int val, volatile void *ptr)

CLREX

void __clrex(void)

PM0056 Datasheet(PDF) 32 Page - STMicroelectronics