PM0056 datasheet(37/156 Pages) STMICROELECTRONICS

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PM0056

The Cortex-M3 processor

If software does not configure any priorities, then all exceptions with a configurable priority

have a priority of 0. For information about configuring exception priorities see

•

System handler priority registers (SHPRx) on page 138

•

Interrupt priority registers (NVIC_IPRx) on page 125

Configurable priority values are in the range 0-15. This means that the Reset, Hard fault,

and NMI exceptions, with fixed negative priority values, always have higher priority than any

other exception.

For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1]

means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted,

IRQ[1] is processed before IRQ[0].

If multiple pending exceptions have the same priority, the pending exception with the lowest

exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending

and have the same priority, then IRQ[0] is processed before IRQ[1].

When the processor is executing an exception handler, the exception handler is preempted

if a higher priority exception occurs. If an exception occurs with the same priority as the

exception being handled, the handler is not preempted, irrespective of the exception

number. However, the status of the new interrupt changes to pending.

2.3.6

Interrupt priority grouping

To increase priority control in systems with interrupts, the NVIC supports priority grouping.

This divides each interrupt priority register entry into two fields:

•

An upper field that defines the group priority

•

A lower field that defines a subpriority within the group.

Only the group priority determines preemption of interrupt exceptions. When the processor

is executing an interrupt exception handler, another interrupt with the same group priority as

the interrupt being handled does not preempt the handler,

If multiple pending interrupts have the same group priority, the subpriority field determines

the order in which they are processed. If multiple pending interrupts have the same group

priority and subpriority, the interrupt with the lowest IRQ number is processed first.

For information about splitting the interrupt priority fields into group priority and subpriority,

see Application interrupt and reset control register (SCB_AIRCR) on page 134.

PM0056 Datasheet(PDF) 37 Page - STMicroelectronics