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PM0056 Datasheet(PDF) 97 Page - STMicroelectronics

Part # PM0056
Description  This programming manual provides information
PDF  156 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PM0056 Datasheet(HTML) 97 Page - STMicroelectronics

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PM0056
The Cortex-M3 instruction set
Condition flags
These instructions do not change the flags.
Examples
ADR.W
R0, BranchTable_Byte
TBB
[R0, R1]
; R1 is the index, R0 is the base address of the
; branch table
Case1
; an instruction sequence follows
Case2
; an instruction sequence follows
Case3
; an instruction sequence follows
BranchTable_Byte
DCB
0
; Case1 offset calculation
DCB
((Case2-Case1)/2)
; Case2 offset calculation
DCB
((Case3-Case1)/2)
; Case3 offset calculation
TBH
[PC, R1, LSL #1]
; R1 is the index, PC is used as base of the
; branch table
BranchTable_H
DCI
((CaseA - BranchTable_H)/2)
; CaseA offset calculation
DCI
((CaseB - BranchTable_H)/2)
; CaseB offset calculation
DCI
((CaseC - BranchTable_H)/2)
; CaseC offset calculation
CaseA
; an instruction sequence follows
CaseB
; an instruction sequence follows
CaseC
; an instruction sequence follows
3.9
Miscellaneous instructions
Table 32 shows the remaining Cortex-M3 instructions:
Table 32. Miscellaneous instructions
Mnemonic
Brief description
See
BKPT
Breakpoint
BKPT on page 98
CPSID
Change Processor State, Disable Interrupts
CPS on page 98
CPSIE
Change Processor State, Enable Interrupts
CPS on page 98
DMB
Data Memory Barrier
DMB on page 99
DSB
Data Synchronization Barrier
DSB on page 100
ISB
Instruction Synchronization Barrier
ISB on page 100
MRS
Move from special register to register
MRS on page 100
MSR
Move from register to special register
MSR on page 101



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