PM0056 datasheet(76/156 Pages) STMICROELECTRONICS

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The Cortex-M3 instruction set

PM0056

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DocID15491 Rev 5

Condition flags

If S is specified, these instructions:

•

Update the N and Z flags according to the result

•

Can update the C flag during the calculation of operand2 (see Flexible second operand

on page 52)

•

Do not affect the V flag

Examples

ANDR9, R2,#0xFF00

ORREQR2, R0, R5

ANDSR9, R8, #0x19

EORSR7, R11, #0x18181818

BICR0, R1, #0xab

ORNR7, R11, R14, ROR #4

ORNSR7, R11, R14, ASR #32

3.5.3

ASR, LSL, LSR, ROR, and RRX

Arithmetic shift right, logical shift left, logical shift right, rotate right, and rotate right with

extend.

Syntax

op{S}{cond} Rd, Rm, Rs

op{S}{cond} Rd, Rm, #n

RRX{S}{cond} Rd, Rm

where:

•

‘op’ is one of:

ASR: Arithmetic shift right

LSL: Logical shift left

LSR: Logical shift right

ROR: Rotate right

•

‘S’ is an optional suffix. If S is specified, the condition code flags are updated on the

result of the operation (see Conditional execution on page 57)

•

‘Rd’ is the destination register

•

‘Rm’ is the register holding the value to be shifted

•

‘Rs’ is the register holding the shift length to apply to the value Rm. Only the least

significant byte is used and can be in the range 0 to 255.

•

‘n’ is the shift length. The range of shift lengths depend on the instruction as follows:

ASR: Shift length from 1 to 32

LSL: Shift length from 0 to 31

LSR: Shift length from 1 to 32

ROR: Shift length from 1 to 31

Note:

MOV{S}{cond} Rd, Rm is the preferred syntax for LSL{S}{cond} Rd, Rm, #0.

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