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PM0056 Datasheet(PDF) 71 Page - STMicroelectronics

Part # PM0056
Description  This programming manual provides information
PDF  156 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PM0056 Datasheet(HTML) 71 Page - STMicroelectronics

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PM0056
The Cortex-M3 instruction set
Restrictions
In these instructions:
•
Do not use PC
•
Do not use SP for Rd and Rt
•
For STREX, Rd must be different from both Rt and Rn
•
The value of offset must be a multiple of four in the range 0-1020
Condition flags
These instructions do not change the flags.
Examples
MOVR1, #0x1; initialize the ‘lock taken’ value try
LDREXR0, [LockAddr]; load the lock value
CMPR0, #0; is the lock free?
ITTEQ; IT instruction for STREXEQ and CMPEQ
STREXEQR0, R1, [LockAddr]; try and claim the lock
CMPEQR0, #0; did this succeed?
BNEtry; no – try again
; yes – we have the lock
3.4.9
CLREX
Clear exclusive.
Syntax
CLREX{cond}
where:
‘cond’ is an optional condition code (see Conditional execution on page 57)
Operation
Use CLREX to make the next STREX, STREXB, or STREXH instruction write 1 to its destination
register and fail to perform the store. It is useful in exception handler code to force the failure
of the store exclusive if the exception occurs between a load exclusive instruction and the
matching store exclusive instruction in a synchronization operation.
See Synchronization primitives on page 31 for more information.
Condition flags
These instructions do not change the flags.
Examples
CLREX



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