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LT3471

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APPLICATIONS INFORMATION

Soft-Start and Shutdown Features

To shut down the part, ground both SHDN/SS pins. To

shut down one switcher but not the other one, ground that

switcher’s SHDN/SS pin. The soft-start feature provides a

way to limit the inrush current drawn from the supply upon

start-up. To use the soft-start feature for either switcher,

slowly ramp up that switcher’s SHDN/SS pin. The rate of

voltage rise at the output of the switcher’s comparator (A1

or A3 for switcher 1 or switcher 2 respectively) tracks the

rate of voltage rise at the SHDN/SS pin once the SHDN/SS

pin has reached about 1.1V. The soft-start function will

go away once the voltage at the SHDN/SS pin exceeds

1.8V. See the Peak Switch Current vs SHDN/SS Voltage

graph in the Typical Performance Characteristics section.

The rate of voltage rise at the SHDN/SS pin can easily be

controlled with a simple RC network connected between

the control signal and the SHDN/SS pin. Typical values

for the RC network are 4.7kΩ and 0.33μF, giving start-up

times on the order of milliseconds. This RC time constant

can be adjusted to give different start-up times. If differ-

ent values of resistance are to be used, keep in mind the

SHDN/SS Current vs SHDN/SS voltage graph along with

the Peak Switch Current vs SHDN/SS Voltage graph, both

found in the Typical Performance Characteristics section.

The impedance looking into the SHDN/SS pin depends

on whether the SHDN/SS is above or below VIN. Normally

SHDN/SS will not be driven above VIN, and thus the imped-

ance looks like 100kΩ in series with a diode. If the voltage

of the SHDN/SS pin is above VIN, the impedance looks

more like 50kΩ in series with a diode. This 100kΩ or 50kΩ

impedance can have a slight effect on the start-up time if

you choose the R in the RC soft-start network too large.

Another consideration is selecting the soft-start time so

that the soft-start feature is dominated by the RC network

and not the capacitor on VREF. (See VREF voltage reference

section of the Applications Information for details.)

The soft-start feature is of particular importance in ap-

plications where the switch will see voltage levels of 30V

or higher. In these applications, the simultaneous presence

of high current and voltage during startup may cause an

overstress condition to the switch. Therefore, depending

on input and output voltage conditions, higher RC time

constant values may be necessary to improve the rug-

gedness of the design.

CAPACITOR SELECTION

Low ESR (equivalent series resistance) capacitors should

be used at the output to minimize the output ripple voltage.

Multi-layer ceramic capacitors are an excellent choice,

as they have extremely low ESR and are available in very

small packages. X5R dielectrics are preferred, followed

by X7R, as these materials retain the capacitance over

wide voltage and temperature ranges. A 4.7μF to 15μF

output capacitor is sufﬁcient for most applications, but

systems with very low output currents may need only a

1μF or 2.2μF output capacitor. Solid tantalum or OS-CON

capacitors can be used, but they will occupy more board

area than a ceramic and will have a higher ESR. Always

use a capacitor with a sufﬁcient voltage rating.

Ceramic capacitors also make a good choice for the input

decoupling capacitor, which should be placed as close as

possible to the LT3471. A 4.7μF to 10μF input capacitor

is sufﬁcient for most applications. Table 2 shows a list

of several ceramic capacitor manufacturers. Consult the

manufacturers for detailed information on their entire

selection of ceramic parts.

Table 2. Ceramic Capacitor Manufacturers

Taiyo Yuden

(408) 573-4150

www.t-yuden.com

AVX

(803) 448-9411

www.avxcorp.com

Murata

(714) 852-2001

www.murata.com

The decision to use either low ESR (ceramic) capacitors

or the higher ESR (tantalum or OS-CON) capacitors can

affect the stability of the overall system. The ESR of any

capacitor, along with the capacitance itself, contributes

a zero to the system. For the tantalum and OS-CON ca-

pacitors, this zero is located at a lower frequency due to

the higher value of the ESR, while the zero of a ceramic

capacitor is at a much higher frequency and can generally

be ignored.

A phase lead zero can be intentionally introduced by placing

a capacitor (CPL) in parallel with the resistor (R3) between

VOUT and VFB as shown in Figure 2. The frequency of the

zero is determined by the following equation.

ƒZ =

2π •R3 • CPL

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