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STM32F2 and STM32F4 practical measurements

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Note:

These timing measurements are considered based on the optimum ART configuration:

(Data+Instruction) cache ON, Prefetch OFF, which results in the best ADC noise immunity.

In other ART configurations, these measurements could result in a difference of a few

cycles.

Note:

3.4

Measurement conclusion

Following the previous results, we can conclude that, in order to obtain the most accurate

conversion results when using the STM32F2/F405/F415/F407/F417 ADC, care must be

taken to configure the ART Flash memory accelerator accordingly. This configuration must

be (Data+Instruction) ON and prefetch OFF to achieve the best accuracy by limiting the

internal noise generated by the Flash.

This section shows how you can choose the best trade-off between A/D conversion

accuracy and the required A/D conversion speed.

For example, the measurements given above demonstrate that, with a 12-bit ADC

resolution, +- 5 LSB can be achieved using an averaging by 4 algorithm (0.6 Msps) when

the ART Flash memory accelerator is configured with (Data+Instruction) ON and prefetch

OFF.

Table 5. Time needed to compute averaging

Computation

time

1. Computation = time taken to add the N samples and divide them by N.

Averaging by 6 (1) Averaging by 8 (1)

Averaging by 8,

2. Computation = time taken to sort the 8 ADC samples, delete the 4 dispersed ones, add the other 4

samples and divide them by 4. This result depends on the sorting algorithm (in this case, the sorting

algorithm is based on successive permutation, which is not optimized for speed).

3. CPU frequency is 144 MHz, as described in Section 3.1.1.

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