DocID022945 Rev 5

19/32

AN4073

STM32F4 ADC accuracy options

31

This could be activated by setting the ADCxDC2 (bit 16 - bit18) in the SYSCFG_PMC

register.

Warning:

These bits can only be set at the following conditions:

- Minimum ADC clock is 30MHz.

- Only one ADCxDC2 bit must be selected in case ADC

conversion does not start at the same time and different

sampling times are used.

- ADC resolution should be equal to 12 bits.

- This bit must not be set when the ADCDC1 bit in PWR_CR

register is set.

In this option, one bit for each ADC is available in SYSCFG_PMC register. There is more

flexibility to enable or not this option for each ADC separately.

As stated in the warning above, these three bits should not be activated simultaneously in

some conditions.

Following are the ADC modes versus the simultaneously usage of ADCxDC2 bits:

For more details about the exact firmware sequence to enable Option 2, please refer to

Section C.2: Option 2.

The ADC accuracy when activating this option will be detailed in the next section.

4.2

Practical measurements

In this section, practical ADC measurements are done in order to demonstrate the impact of

these ADC accuracy options.

Table 6. ADCxDC2 usage versus ADC mode

Single

mode

(1)

Multi ADC Modes

Injected

simultaneous

Regular

simultaneous

Interleaved

Alternate

trigger

Injected

simultaneous

+ Regular

simultaneous

Regular

simultaneous

+ Alternate

trigger

One

ADCxDC2

YES

YES

YES

YES

YES

YES

YES

Some or all

ADCxDC2

NO

(2)

(2)

NO

(3)

(2)

(2)

1. When two or three ADCs are activated separately and each one is configured in single mode, only one ADCxDC2 bit

should be used.

2. Some or all ADCxDC2 bits could be used in case the same sampling time is used for all ADCs.

3. Some or all ADCxDC2 bits could be used in case the start of conversion triggers are controlled to set up an interval

between each ADC end of sampling equal to or greater than 15 ADC cycles.