Specifications ispLSI 1024/883

5

External Timing Parameters

Over Recommended Operating Conditions

MIN. MAX.

Data Propagation Delay, 4PT bypass, ORP bypass

Data Propagation Delay, Worst Case Path

Clock Frequency with External Feedback

GLB Reg. Setup Time before Clock, 4PT bypass

GLB Reg. Clock to Output Delay, ORP bypass

GLB Reg. Hold Time after Clock, 4 PT bypass

GLB Reg. Setup Time before Clock

GLB Reg. Clock to Output Delay

GLB Reg. Hold Time after Clock

Ext. Reset Pin to Output Delay

Ext. Reset Pulse Duration

Input to Output Enable

Input to Output Disable

Ext. Sync. Clock Pulse Duration, High

Ext. Sync. Clock Pulse Duration, Low

I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)

I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)

ns

ns

MHz

MHz

MHz

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

A

A

A

–

–

–

A

–

–

–

–

A

–

B

C

–

–

–

–

PARAMETER

#

2

UNITS

COND.

1

tsu2 + tco1

(

)

–

–

60

38

83

9

–

0

13

–

0

–

13

–

–

6

6

2.5

8.5

20

25

–

–

–

–

13

–

–

16

–

22.5

–

24

24

–

–

–

–

-60

Table 2-0030-24 mil

1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-Bit loadable counter using GRP feedback.

4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.

5. Reference Switching Test Conditions Section.