In-System Programmable High Density PLD

1

1024MIL_01

Features

• HIGH-DENSITY PROGRAMMABLE LOGIC

— High-Speed Global Interconnect

— 4000 PLD Gates

— 48 I/O Pins, Six Dedicated Inputs

— 144 Registers

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Fast Random Logic

— Security Cell Prevents Unauthorized Copying

—

—

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— 100% Tested

• IN-SYSTEM PROGRAMMABLE

— In-System Programmable™ (ISP™) 5-Volt Only

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

• COMBINES EASE OF USE AND THE FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEX-

IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

unctional

Block Diagram

Output Routing Pool

CLK

B0 B1 B2 B3 B4 B5 B6 B7

A0

A1

A2

A3

A4

A5

A6

A7

C7

C6

C5

C4

C3

C2

C1

C0

Global Routing Pool (GRP)

Logic

Array

DQ

DQ

DQ

DQ

GLB

0139-A-isp

Description

The ispLSI 1024/883 is a High-Density Programmable

Logic Device processed in full compliance to MIL-STD-

883. This military grade device contains 144 Registers,

48 Universal I/O pins, six Dedicated Input pins, four

Dedicated Clock Input pins and a Global Routing Pool

(GRP). The GRP provides complete interconnectivity

between all of these elements. The ispLSI 1024/883

features 5-Volt in-system programmability and in-system

diagnostic capabilities. It is the first device which offers

non-volatile reprogrammability of the logic, as well as the

interconnect to provide truly reconfigurable systems.

The basic unit of logic on the ispLSI 1024/883 device is

the Generic Logic Block (GLB). The GLBs are labeled A0,

A1 .. C7 (see figure 1). There are a total of 24 GLBs in the

ispLSI 1024/883 device. Each GLB has 18 inputs, a

programmable AND/OR/XOR array, and four outputs

which can be configured to be either combinatorial or

registered. Inputs to the GLB come from the GRP and

dedicated inputs. All of the GLB outputs are brought back

into the GRP so that they can be connected to the inputs

of any other GLB on the device.

Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

September 2000

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Functional Block Diagram