Specifications ispLSI 1024/883

7

ns

ns

ns

ns

ns

ns

ns

ns

ns

–

–

–

6.0

4.6

1.3

4.6

1.3

–

4.0

6.7

6.7

6.0

7.3

6.6

7.3

6.6

12.0

Outputs

Clocks

Global Reset

47

48

49

50

51

52

53

54

55

Output Buffer Delay

I/O Cell OE to Output Enabled

I/O Cell OE to Output Disabled

Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)

Clock Delay, Y1 or Y2 to Global GLB Clock Line

Clock Delay, Clock GLB to Global GLB Clock Line

Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line

Clock Delay, Clock GLB to I/O Cell Global Clock Line

Global Reset to GLB and I/O Registers

MIN. MAX.

DESCRIPTION

PARAMETER

UNITS

-60

#

2

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.