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UPD75402ACT Datasheet(PDF) 34 Page - NEC

Part # UPD75402ACT
Description  4 BIT SINGLE-CHIP MICROCOMPUTER
PDF  48 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD75402ACT Datasheet(HTML) 34 Page - NEC

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µPD75402A(A)
SBI mode (SCK ··· Internal clock output (master)):
SBI mode (SCK ··· External clock input (slave)):
Note RL and CL are the resistance and capacitance of the SO output line load respectively.
Min.
1600
3800
tKCY3/2 – 50
tKCY3/2 – 150
150
tKCY3/2
0
0
tKCY3
tKCY3
tKCY3
tKCY3
Parameter
SCK cycle time
SCK high/low level
width
SB0 setup time
(referred to SCK
↑)
SB0 hold time
(referred to SCK
↑)
Delay from SCK
↓ to
SB0 output
Delay from SCK
↑ to SB0↓
Delay from SB0
↓ to SCK↓
SB0 low-level width
SB0 high-level width
Symbol
tKCY4
tKL4
tKH4
tSIK4
tKSI4
tKSO4
tKSB
tSBK
tSBL
tSBH
Symbol
tKCY3
tKL3
tKH3
tSIK3
tKSI3
tKSO3
tKSB
tSBK
tSBL
tSBH
Parameter
SCK cycle time
SCK high/low level
width
SB0 setup time
(referred to SCK
↑)
SB0 hold time
(referred to SCK
↑)
Delay from SCK
↓ to
SB0 output
Delay from SCK
↑ to SB0↓
Delay from SB0
↓ to SCK
SB0 low-level width
SB0 high-level width
Typ.
Max.
250
1000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
Conditions
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
RL = 1 k
Ω,
CL = 100 pF Note
VDD = 4.5 to 6.0 V
Min.
800
3200
400
1600
100
tKCY4/2
0
0
tKCY4
tKCY4
tKCY4
tKCY4
Typ.
Max.
300
1000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns



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