UPD75402ACT datasheet(15/48 Pages) NEC

15 / 48 page

µPD75402A(A)

5.2

CLOCK GENERATOR

Operation of the clock generator is specified by the processor clock control register (PCC).

The instruction execution time is variable.

• 0.95

µs, 1.91 µs, 15.3 µs (when fXX is 4.19 MHz.)

Fig. 5-1 Block Diagram of the Clock Generator

VDD

System

clock

oscillator

fXX or fX

Oscillation

stops.

1/16 to 1/512

Frequency divider

1/2 1/16











Frequency

divider

HALT flip-

flop

RESET input rising edge

detection signal

RESET input falling

edge detection signal

Standby release signal

from interrupt control circuit

STOP flip-

flop

All bits are

cleared.

PCC2 is

cleared.

HALT*

STOP*

PCC0

PCC1

PCC2

PCC3

PCC

· Basic interval timer (BT)

· Clock output circuit

· Serial interface

1/4

· INT0 noise eliminator











· CPU

· INT0 noise

eliminator

· Clock output

circuit

Remarks 1. fXX = Crystal/ceramic oscillated frequency

2. fX = External clock frequency

Φ = CPU clock

4. An asterisk (*) indicates instruction execution.

5. PCC: Processor clock control register

6. One clock cycle (tCY) of

Φ is equal to one machine cycle of an instruction. See AC

characteristics of Chapter 10 for details of tCY.

UPD75402ACT Datasheet(PDF) 15 Page - NEC

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