UPD75402ACT datasheet(8/48 Pages) NEC

8 / 48 page

µPD75402A(A)

3.2

NON-PORT PINS

Remark See Chapter 8 for each pin status during resetting.

Note Connect the NC pin directly to the VSS pin when the

µPD75402A(A) shares the printed circuit board

with the

µPD75P402 in emulation.

3.3

PIN INPUT/OUTPUT CIRCUITS

The I/O circuits of the

µPD75402A(A) are roughly shown on the next and subsequent pages.

Table 1-1 I/O Circuit Type of Pin

Remark The types in circles have a Schmitt-triggered input.

INT0

INT2

SCK

SB0

PCL

X1, X2

RESET

VDD

VSS

NC Note

I/O

Input

I/O

Input

–

Dual-

function pin

P10

P12

P03

P02/SB0

P01

P02/SO

P22

–

Function

Edge detection vectored interrupt request input pin (A detected edge

can be selected by the mode register.)

Connects with the built-in noise eliminator using a sampling clock.

Edge detection external test input pin (A rising edge is detected.)

Serial data input pin

Serial data output pin

Serial clock I/O pin

Serial bus I/O pin

Clock output pin

Pin for connection to a crystal/ceramic resonator for system clock

generation. An external clock is applied to X1, and its reverse phase to

X2.

System reset input pin, which connects with the built-in noise elimina-

tor using an analog delay.

Positive power supply pin

Ground potential pin

No connection

P00

P01 /SCK

P02 / SO / SB0

P03 / SI

P10 / INT0

P12 /INT2

P20, P21, and P23

P22 /PCL

P30 - P33

P50 - P53

P60 - P63

RESET

I/O type

E-B

I /O type

-A

-B

-C

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