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LT1816 Datasheet(PDF) 13 Page - Linear Technology

Part # LT1816
Description  Single/Dual/Quad 220MHz, 1500V/s Operational Amplifiers with Programmable Supply Current
PDF  20 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LT1816 Datasheet(HTML) 13 Page - Linear Technology

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LT1815/LT1816/LT1817
13
181567fb
APPLICATIONS INFORMATION
Power Dissipation
The LT1815/LT1816/LT1817 combine high speed and large
output drive in small packages. It is possible to exceed
the maximum junction temperature specification (150°C)
under certain conditions. Maximum junction temperature
(TJ)iscalculatedfromtheambienttemperature(TA),power
dissipation per amplifier (PD) and number of amplifiers
(n) as follows:
TJ = TA + (n • PD • θJA)
Power dissipation is composed of two parts. The first is
due to the quiescent supply current and the second is due
to on-chip dissipation caused by the load current. The
worst-case load induced power occurs when the output
voltage is at one-half of either supply voltage (or the
maximum swing if less than one-half the supply voltage).
Therefore, PDMAX is:
PDMAX = (V+ – V–) • (ISMAX) + (V+/2)2/RL or
PDMAX = (V+ – V–) • (ISMAX) + (V+ – VOMAX) • (VOMAX/RL)
Example: LT1816IS8 at 85°C, VS = ±5V, RL=100Ω
PDMAX = (10V) • (11.5mA) + (2.5V)2/100Ω = 178mW
TJMAX = 85°C + (2 • 178mW) • (150°C/W) = 138°C
Circuit Operation
The LT1815/LT1816/LT1817 circuit topology is a true volt-
age feedback amplifier that has the slewing behavior of a
current feedback amplifier. The operation of the circuit can
be understood by referring to the Simplified Schematic.
Complementary NPN and PNP emitter followers buffer
the inputs and drive an internal resistor. The input volt-
age appears across the resistor, generating current that
is mirrored into the high impedance node.
Complementary followers form an output stage that buf-
fers the gain node from the load. The input resistor, input
stage transconductance and the capacitor on the high
impedance node determine the bandwidth. The slew rate
is determined by the current available to charge the gain
node capacitance. This current is the differential input
voltage divided by R1, so the slew rate is proportional to
the input step. Highest slew rates are therefore seen in
the lowest gain configurations.
Figure 1. Programming Resistor Between ISET and V–
Figure 2. Gain Bandwidth Product vs RSET Programming Resistor
Figure 3. Supply Current vs RSET Programming Resistor
ISET
V–
181567 F01
V+
RSET
–5V
5V
–
+
LT1815S6
RSET PROGRAMING RESISTOR (Ω)
50
100
150
200
250
10
1k
10k
40k
181567 F02
0
100
VS = 5V
TA = 25°C
RL = 500Ω
RL = 100Ω
RSET PROGRAMMING RESISTOR (Ω)
2
4
6
7
10
1k
10k
40k
181567 F03
0
100
5
3
1
VS = ±5V
TA = 25°C
PER AMPLIFIER



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