LTC1709 datasheet(19/28 Pages) LINER

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LTC1709

The output of the phase detector is a complementary pair

of current sources charging or discharging the external

filter network on the PLLFLTR pin. A simplified block

diagram is shown in Figure 7.

If the external frequency (fPLLIN) is greater than the oscil-

lator frequency f0SC, current is sourced continuously,

pulling up the PLLFLTR pin. When the external frequency

is less than f0SC, current is sunk continuously, pulling

down the PLLFLTR pin. If the external and internal fre-

quencies are the same but exhibit a phase difference, the

current sources turn on for an amount of time correspond-

ing to the phase difference. Thus the voltage on the

PLLFLTR pin is adjusted until the phase and frequency of

the external and internal oscillators are identical. At this

stable operating point the phase comparator output is

open and the filter capacitor CLP holds the voltage. The

LTC1709 PLLIN pin must be driven from a low impedance

source such as a logic gate located close to the pin.

The loop filter components (CLP, RLP) smooth out the

current pulses from the phase detector and provide a

stable input to the voltage controlled oscillator. The filter

components CLP and RLP determine how fast the loop

acquires lock. Typically RLP =10kΩ and CLP is 0.01µF to

0.1

µF.

APPLICATIO S I FOR ATIO

Figure 7. Phase-Locked Loop Block Diagram

Figure 6, eliminates any extra supply current during shut-

down while eliminating the INTVCC loading from prevent-

ing controller start-up.

Why should you defeat current latchoff? During the

prototyping stage of a design, there may be a problem with

noise pickup or poor layout causing the protection circuit

to latch off the controller. Defeating this feature allows

troubleshooting of the circuit and PC layout. The internal

short-circuit and foldback current limiting still remains

active, thereby protecting the power supply system from

failure. A decision can be made after the design is com-

plete whether to rely solely on foldback current limiting or

to enable the latchoff feature by removing the pull-up

resistor.

The value of the soft-start capacitor CSS may need to be

scaled with output voltage, output capacitance and load

current characteristics. The minimum soft-start capaci-

tance is given by:

CSS > (COUT )(VOUT)(10-4)(RSENSE)

The minimum recommended soft-start capacitor of CSS =

0.1

µF will be sufficient for most applications.

Phase-Locked Loop and Frequency Synchronization

The LTC1709 has a phase-locked loop comprised of an

internal voltage controlled oscillator and phase detector.

This allows the top MOSFET turn-on to be locked to the

rising edge of an external source. The frequency range of

the voltage controlled oscillator is

±50% around the

center frequency fO. A voltage applied to the PLLFLTR pin

of 1.2V corresponds to a frequency of approximately

220kHz. The nominal operating frequency range of the

LTC1709 is 140kHz to 310kHz.

The phase detector used is an edge sensitive digital type

which provides zero degrees phase shift between the

external and internal oscillators. This type of phase detec-

tor will not lock up on input frequencies close to the

harmonics of the VCO center frequency. The PLL hold-in

range,

∆fH, is equal to the capture range, ∆fC:

∆fH = ∆fC = ±0.5 fO

(150kHz-300kHz)

EXTERNAL

OSC

2.4V

RLP

10k

CLP

OSC

DIGITAL

PHASE/

FREQUENCY

DETECTOR

PHASE

DETECTOR

PLLIN

1709 F07

PLLFLTR

50k

Minimum On-Time Considerations

Minimum on-time tON(MIN) is the smallest time duration

that the LTC1709 is capable of turning on the top MOSFET.

It is determined by internal timing delays and the gate

charge required to turn on the top MOSFET. Low duty cycle

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