Low-Cost, 2-Channel, ±14-Bit Serial ADCs

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15

NO-OP is a zero, the control word is not transferred to

the control register, the ADC’s configuration remains

unchanged, and no new conversion is initiated. This

allows specific ADCs in a “daisy chain” arrangement to

be reconfigured while leaving the remaining ADCs

unchanged. Table 1 lists the various ADC control word

functions.

Output data is shifted out of DOUT at the same time the

input control word for the next conversion is shifted in

(Figure 8).

On power-up, all internal registers reset to zero.

Therefore, when writing the first control word to the

ADC, the data simultaneously shifted out will be zeros.

The first conversion begins when CS goes high (NO-OP

= 1). The results are placed in the 16-bit I/O register for

access on the next data-transfer operation.

Power-Down Mode

Bits 0 and 1 control the ADC’s power-down mode. If bit

0 (PD) is a logic high, power is removed from all analog

circuitry except the RC oscillator. A logic high at bit 1

(PDX) removes power from the RC oscillator. If both bits

PD and PDX are a logic high, or if PD is high and

RCSEL is low, the supply currents reduce to 4µA. If an

external XCLK clock continues to run in power-down

mode, the supply current will depend on the clock rate.

When PDX is set high, the internal RC oscillator stops

shortly after CS returns high. If the next control word

written to the device has NO-OP = 1 instructing the

ADC to convert, BUSY will go low, but because the RC

oscillator is stopped, BUSY will remain low and will not

allow a new conversion to begin. To avoid this situation,

write a “dummy” control word with NO-OP = 0 and any

combination of bits 14-0 in the control word following

the control word with PDX = 0. With NO-OP = 0, bits 14-

0 are ignored and the internal state machine resets.

Next, perform a normal 3-step calibration (see Table 3).

through a resistor (suggested value is 1M

Ω) when the

resistor is not necessary if the external oscillator mode

is used, or if the internal oscillator is not shut down.

Selecting the Analog Inputs

Bit 4 (CHS) controls which of the two differential inputs

connect to the internal ADC inputs (see the

Functional

Diagram). A logic high selects IN2+ and IN2- while a

logic low selects IN1+ and IN1-. Table 2 shows the

allowable input multiplexer configurations.

Table 1. Input Control-Word Bit Map

↑

First bit clocked in.

PD

PDX

NUL

CAL

CHS

NU

NU

DV2

DV4

CONV1

CONV2

CONV3

CONV4

NU

NU

NO-OP

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Analog Power-Down. Set this bit high to power down the analog section.

PD

0

Oscillator Power-Down. Set this bit high to power down the RC oscillator.

PDX

1

Internal Offset-Null Bit. A logic high selects offset-null mode. See Table 3.

NUL

2

Gain-Calibration Bit. A logic high selects gain-calibration mode. See Table 3.

CAL

3

Input Channel Select. A logic high selects channel 2 (IN2+ and IN2-), while a logic low

selects channel 1 (IN1+ and IN1-). See Tables 2 and 3.

CHS

4

XCLK to Oversampling Cock Ratio Control Bits. See Table 5.

DV2, DV4

7, 8

Conversion Time Control Bits. See Table 4.

CONV1–CONV4

9–12

Used for test purposes only. Set these bits low.

NU

5, 6, 13, 14

If this bit is a logic high, the remaining 15 LSBs are transferred to the control register and a

new conversion begins when CS returns high. If this bit is set low, the control word is not

passed to the control register, the ADC configuration remains unchanged, and no new con-

version begins when CS returns high.

NO-OP

15

DESCRIPTION

NAME

BIT