Single-Supply, Low-Power,

Serial 8-Bit ADCs

10

______________________________________________________________________________________

_______________Detailed Description

The MAX1106/MAX1107 analog-to-digital converters

(ADCs) use a successive-approximation conversion

technique and input track/hold (T/H) circuitry to convert

an analog signal to an 8-bit digital output. A simple ser-

ial interface provides easy interface to microprocessors

(µPs). No external hold capacitors are required. All of

the MAX1106/MAX1107 operating modes are pin con-

figurable: internal or external reference, single-ended

or pseudo-differential unipolar conversion, and power

down. Figure 3 shows the typical operating circuit.

Analog Inputs

Track/Hold

The input architecture of the ADCs is illustrated in

Figure 4’s equivalent-input circuit of and is composed

of the T/H, the input multiplexer, the input comparator,

the switched capacitor DAC, and the auto-zero rail.

The device is in acquisition mode most of the time.

During the acquisition interval, the positive input (IN+)

is tracked and is connected to the holding capacitor

edge of CONVST. At this point the T/H switch opens

IN+. Once conversion is complete the T/H returns

immediately to its tracking mode.

The time required for the T/H to acquire an input signal

is a function of how quickly its input capacitance is

charged. If the input signal’s source impedance is high,

the acquisition time lengthens, and more time must be

allowed between conversions. The acquisition time,

acquired. It is calculated by:

3k

GND

DOUT

GND

3k

DOUT

Figure 1. Load Circuits for Enable Time

3k

GND

DOUT

GND

3k

DOUT

Figure 2. Load Circuits for Disable Time

I/O

SCK (SK)

MISO (SI)

GND

DOUT

SCLK

CONVST

GND

SHDN

IN-

1

µF

0.1

µF

1

µF

ON

OFF

IN+

ANALOG

INPUTS

MAX1106

MAX1107

CPU

REFOUT

REFIN

Figure 3. Typical Operating Circuit

IN-

IN+

REFIN

GND

CAPACITIVE DAC

COMPARATOR

18pF

6.5k

AUTOZERO

RAIL

TRACK

HOLD

Figure 4. Equivalent Input Circuit