MAX113 datasheet(4/12 Pages) MAXIM

4 / 12 page

+3V, 400ksps, 4/8-Channel,

8-Bit ADCs with 1µA Power-Down

_______________________________________________________________________________________

TIMING CHARACTERISTICS

(VDD = +3V, TA = +25°C, unless otherwise noted.) (Note 4)

Note 4: Input control signals are specified with tr = tf = 5ns, 10% to 90% of 3V, and timed from a voltage level of 1.3V. Timing

delays get shorter at higher supply voltages. See the Conversion Time vs. Supply Voltage graph in the

Typical Operating

Characteristics to extrapolate timing delays at other power-supply voltages.

Note 5: See Figure 1 for load circuit. Parameter defined as the time required for the output to cross 0.66V or 2.0V.

Note 6: See Figure 2 for load circuit. Parameter defined as the time required for the data lines to change 0.5V.

Note 7: Also defined as the Minimum Address-Valid to Convert-Start Time.

0.8

0.66

WR Pulse Width

tWR

0.6

µs

700

Minimum

Acquisition Time

tACQ

450

(Note 7)

600

MAX117M

MIN

MAX

MIN

TYP

MAX

PARAMETER

SYMBOL

MIN

MAX

UNITS

CONDITIONS

MAX117C/E

TA = +25°C

ALL GRADES

TA = TMIN to TMAX

250

Data Access Time

(WR-RD Mode)

tACC2

180

tRD > tINTL, CL = 100pF

(Note 5)

220

1.0

600

150

600

400

1.8

250

240

Data Access Time

After

INT

tID

Delay Between

and

RD Pulses

tRD

0.8

µs

RD Pulse Width

(WR-RD Mode)

tREAD1

400

100

Multiplexer Address

Hold Time

Data Access Time

(WR-RD Mode)

tACC1

400

RD to INT Delay

tRI

300

WR to INT Delay

tINTL

0.7

1.45

µs

tAH

Pipelined mode, CL = 100pF

RD Pulse Width

(WR-RD Mode)

tREAD2

180

WR to INT Delay

tIHWR

180

0.9

500

130

tRD > tINTL, determined by

tACC2

tRD < tINTL, determined by

tACC1

500

tRD < tINTL, CL = 100pF

(Note 5)

340

CL = 50pF

Pipelined mode, CL = 50pF

1.6

220

200

150

140

tCRD +

150

180

130

120

tCRD +

130

170

Data Hold Time

tDH

100

CS to RD, WR

Setup Time

tCSS

CS to RD, WR

Hold Time

tCSH

CS to RDY Delay

tRDY

100

(Note 6)

Data Access Time

(RD Mode)

tACC0

tCRD +

100

RD to INT Delay

(RD Mode)

tINTH

100

160

CL = 100pF (Note 5)

CL = 50pF,

RL = 5.1kΩ to VDD

CL = 50pF

2.4

2.06

Conversion Time

(WR-RD Mode)

tCWR

1.8

µs

tRD < tINTL, CL = 100pF

(Note 5)

1.4

1.2

Power-Up Time

tUP

0.9

µs

2.6

2.4

Conversion Time

(RD Mode)

tCRD

2.0

µs

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