+3V, 400ksps, 4/8-Channel,

8-Bit ADCs with 1µA Power-Down

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7

_______________Detailed Description

Converter Operation

The MAX113/MAX117 use a half-flash conversion tech-

nique (see

Functional Diagram) in which two 4-bit flash

ADC sections achieve an 8-bit result. Using 15 com-

parators, the flash ADC compares the unknown input

voltage to the reference ladder and provides the upper

four data bits. An internal digital-to-analog converter

(DAC) uses the four most significant bits (MSBs) to

generate both the analog result from the first flash con-

version and a residue voltage that is the difference

between the unknown input and the DAC voltage. The

residue is then compared again with the flash com-

parators to obtain the lower four data bits (LSBs).

An internal analog multiplexer enables the devices to

read four (MAX113) or eight (MAX117) different analog

voltages under microprocessor (µP) control. One of the

MAX117’s analog channels, IN8, is internally hard-

Power-Down Mode

In burst-mode or low-sample-rate applications, the

MAX113/MAX117 can be shut down between conver-

sions, reducing supply current to microamp levels (see

Typical Operating Characteristics). A logic low on the

PWRDN pin shuts the devices down, reducing supply

current typically to 1µA when powered from a single

+3V supply. A logic high on

PWRDN wakes up the

MAX113/MAX117, and the selected analog input enters

the track mode. The signal is fully acquired after 900ns

(this includes both the power-up delay and the

track/hold acquisition time), and a new conversion can

be started. If the power-down feature is not required,

connect

sumption, keep digital inputs at the supply rails in

power-down mode. Refer to the

Reference section for

information on reducing the reference current during

power-down.

___________________Digital Interface

The MAX113/MAX117 have two basic interface modes,

which are set by the MODE pin. When MODE is low,

the converters are in read mode; when MODE is high,

the converters are set up for write-read mode. The A0,

A1, and A2 inputs control channel selection, as shown

in Table 1. The address must be valid for a minimum

DATA

OUTPUTS

DATA

OUTPUTS

a) HIGH-Z TO VOH

b) HIGH-Z TO VOL

Figure 1. Load Circuits for Data-Access Time Test

DATA

OUTPUTS

10pF

3k

10pF

a) VOH TO HIGH-Z

b) VOL TO HIGH-Z

3k

DATA

OUTPUTS

Figure 2. Load Circuits for Data-Hold Time Test

Table 1. Truth Table for Input Channel

Selection

MAX113

00

IN1

IN2

01

IN4

IN3

11

10

IN6

IN5

——

IN8

IN7

——

——

——

00

1

01

1

01

0

10

1

11

1

11

0

10

0

MAX117

00

0

SELECTED CHANNEL

A2

A1

A0

A1

A0