Detailed Description of the Digital Lines

Chip-Select (CS) and Write-Enable (WE)

CS is used to enable OUT, control serial communica-

tion, and force an update of the configuration and DAC

registers.

• A low on CS disables serial communication and

places OUT in a high-impedance state.

• A transition from low to high on CS forces an update

of the configuration and DAC registers from the

EEPROM when the “U” bit is zero.

• A transition from high to low on CS terminates pro-

gramming mode.

• A logic high on CS enables OUT and serial commu-

nication (see

Communication Protocol section).

WE controls the refresh rate for the internal configura-

tion and DAC registers from the EEPROM and enables

the erase/write operations. If communication has been

initiated (see

Communication Protocol section), internal

register refresh is disabled.

• A low on WE disables the erase/write operations and

also disables register refreshing from the EEPROM.

• A high on WE selects a refresh rate of approximately

400 times per second and enables EEPROM

erase/write operations.

after the MAX1458 EEPROM has been programmed.

SCLK (Serial Clock)

SCLK must be driven externally and is used to input

commands to the MAX1458 and read EEPROM con-

tents. Input data on DIO is latched on the rising edge of

SCLK. Noise on SCLK may disrupt communication. In

noisy environments, place a capacitor (0.01µF)

Data Input/Output (DIO)

The DIO line is an input/output pin used to issue com-

mands to the MAX1458 (input mode) or read the

EEPROM contents (output mode).

In input mode (the default mode), data on DIO is

latched on each rising edge of SCLK. Therefore, data

on DIO must be stable at the rising edge of SCLK and

should transition on the falling edge of SCLK.

DIO will switch to output mode after receiving a “READ

EEPROM” command, and will return the data bit

addressed by the digital value in the “READ EEPROM”

command. After a low-to-high transition or CS, DIO

returns to input mode and is ready to accept more

commands.

Communication Protocol

To initiate communication, the first six bits on DIO after

CS transitions from low to high must be 1010U0

(defined as the INIT SEQUENCE). The MAX1458 will

then begin accepting 16-bit control words (Figure 4).

If the INIT SEQUENCE is not detected, all subsequent

data on DIO is ignored until CS again transitions from

low to high and the correct INIT SEQUENCE is received.

The “U” bit of the INIT SEQUENCE controls the updat-

ing of the DACs and configuration register from the

internal EEPROM. If this bit is low (U = 0), all four inter-

nal DACs and the configuration register will be updated

from the EEPROM on the next rising edge of CS (this is

also the default on power-up). If the “U” bit is high, the

DACs and configuration register will not be updated

from the internal EEPROM; they will retain their current

value on any subsequent CS rising edge. The

MAX1458 continues to accept control words until CS is

brought low.

1%-Accurate, Digitally Trimmed

Sensor Signal Conditioner

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9

Figure 4. Communication Sequence

CS

SCLK

DIO

16 CLK

CYCLES

BEGIN

PROGRAMMING

SEQUENCE

CONTROL

WORD

CONTROL

WORD

CONTROL

WORDS

16 CLK

CYCLES

n x 16 CLK

CYCLES

X

1

0

1

D0

D0

D1

D1

CM3

CM3

0

U

0