MAX1652EEE datasheet(15/28 Pages) MAXIM

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High-Efficiency, PWM, Step-Down

DC-DC Controllers in 16-Pin QSOP

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In discontinuous (light-load) mode, the synchronous

switch is turned off as the inductor current falls through

zero. The synchronous rectifier works under all operat-

ing conditions, including idle mode. The synchronous-

switch timing is further controlled by the secondary

feedback (SECFB) signal in order to improve multiple-

output cross-regulation (see

Secondary Feedback-

Regulation Loop section).

Internal VL and REF Supplies

An internal regulator produces the 5V supply (VL) that

powers the PWM controller, logic, reference, and other

blocks. This +5V low-dropout linear regulator can sup-

ply up to 5mA for external loads, with a reserve of

20mA for gate-drive power. Bypass VL to GND with

4.7µF. Important: VL must not be allowed to exceed

5.5V. Measure VL with the main output fully loaded. If

VL is being pumped up above 5.5V, the probable

cause is either excessive boost-diode capacitance or

excessive ripple at V+. Use only small-signal diodes for

D2 (10mA to 100mA Schottky or 1N4148 are preferred)

and bypass V+ to PGND with 0.1µF directly at the

package pins.

The 2.5V reference (REF) is accurate to ±1.6% over

temperature, making REF useful as a precision system

reference. Bypass REF to GND with 0.33µF minimum.

REF can supply up to 1mA for external loads. However,

if tight-accuracy specs for either VOUT or REF are

essential, avoid loading REF with more than 100µA.

Loading REF reduces the main output voltage slightly,

according to the reference-voltage load regulation

error. In MAX1654 applications, ensure that the SECFB

divider doesn’t load REF heavily.

When the main output voltage is above 4.5V, an internal

P-channel MOSFET switch connects CSL to VL while

simultaneously shutting down the VL linear regulator.

This action bootstraps the IC, powering the internal cir-

cuitry from the output voltage, rather than through a lin-

ear regulator from the battery. Bootstrapping reduces

power dissipation caused by gate-charge and quies-

cent losses by providing that power from a 90%-effi-

cient switch-mode source, rather than from a less

efficient linear regulator.

It’s often possible to achieve a bootstrap-like effect,

even for circuits that are set to VOUT < 4.5V, by power-

ing VL from an external-system +5V supply. To achieve

this pseudo-bootstrap, add a Schottky diode between

the external +5V source and VL, with the cathode to the

VL side. This circuit provides a 1% to 2% efficiency

boost and also extends the minimum battery input to

less than 4V. The external source must be in the range

of 4.8V to 5.5V.

Boost High-Side

Gate-Driver Supply (BST Pin)

Gate-drive voltage for the high-side N-channel switch is

generated by a flying-capacitor boost circuit as shown

in Figure 5. The capacitor is alternately charged from

the VL supply and placed in parallel with the high-side

MOSFET’s gate-source terminals.

On start-up, the synchronous rectifier (low-side MOS-

FET) forces LX to 0V and charges the BST capacitor to

5V. On the second half-cycle, the PWM turns on the

high-side MOSFET by closing an internal switch

between BST and DH. This provides the necessary

enhancement voltage to turn on the high-side switch,

REF

CSH

CSL

SLOPE COMPENSATION

TO PWM

LOGIC

OUTPUT DRIVER

UNCOMPENSATED

HIGH-SPEED

LEVEL TRANSLATOR

AND BUFFER

Figure 4. Main PWM Comparator Block Diagram

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