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MAX1652EEE Datasheet(PDF) 25 Page - Maxim Integrated Products |
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MAX1652EEE Datasheet(HTML) 25 Page - Maxim Integrated Products |
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25 / 28 page ![]() of top-layer copper, so that they don’t go through vias. The resulting top-layer “sub-ground-plane” is connected to the normal inner-layer ground plane at the output ground terminals. This ensures that the analog GND of the IC is sensing at the output termi- nals of the supply, without interference from IR drops and ground noise. Other high-current paths should also be minimized, but focusing ruthlessly on short ground and current-sense connections eliminates about 90% of all PC board layout diffi- culties. See the evaluation kit PC board layouts for examples. 2) Place the IC and signal components. Keep the main switching node (LX node) away from sensitive ana- log components (current-sense traces and REF and SS capacitors). Placing the IC and analog compo- nents on the opposite side of the board from the power-switching node is desirable. Important: the IC must be no farther than 10mm from the current- sense resistor. Keep the gate-drive traces (DH, DL, and BST) shorter than 20mm and route them away from CSH, CSL, REF, and SS. 3) Employ a single-point star ground where the input ground trace, power ground (subground plane), and normal ground plane all meet at the output ground terminal of the supply. High-Efficiency, PWM, Step-Down DC-DC Controllers in 16-Pin QSOP ______________________________________________________________________________________ 25 MAX1652 MAX1653 MAX1654 MAX1655 SENSE RESISTOR MAIN CURRENT PATH FAT, HIGH-CURRENT TRACES Figure 9. Kelvin Connections for the Current-Sense Resistor 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 DH LX BST DL GND REF (SECFB) SKIP SS TOP VIEW MAX1652 MAX1653 MAX1654 MAX1655 PGND VL V+ CSL ( ) ARE FOR MAX1652/MAX1654. CSH FB SHDN SYNC QSOP 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 DH LX BST DL GND REF SKIP SS MAX1653 MAX1655 PGND VL V+ CSL CSH FB SHDN SYNC Narrow SO Pin Configurations |
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