Detailed Description

The MAX1970/MAX1971/MAX1972 are dual-output,

fixed-frequency, current-mode, PWM, step-down

DC/DC converters. The MAX1970 and MAX1972 switch

at 1.4 MHz while the MAX1971 switches at 700kHz. The

two converters on each IC switch 180° out of phase

with each other to reduce input ripple current. The

high-switching frequency allows use of smaller capaci-

tors for filtering and decoupling. Internal synchronous

rectifiers improve efficiency and eliminate the typical

Schottky freewheeling diode. The on-resistances of the

internal MOSFETs are used to sense the switch cur-

rents for controlling and protecting the MOSFETs, elimi-

nating current-sensing resistors to further improve

efficiency and cost.

The input voltage range is 2.6V to 5.5V. Each converter

has a three-mode feedback input. Internally, OUT1 is

set to either 3.3V or 1.8V, and OUT2 to 2.5V or 1.5V by

respectively. When FBSEL1 or FBSEL2 are floating,

each output can be set to any voltage between 1.2V

output below 1.2V is also possible (see the Output

Voltage Selection section).

DC-DC Controller

The MAX1970/MAX1971/MAX1972 family of step-down

converters uses a pulse-width-modulating (PWM) current-

mode control scheme. The heart of the current-mode

PWM controller is an open-loop comparator that com-

pares the integrated voltage-feedback signal against

the sum of the amplified current-sense signal and the

slope compensation ramp. At each rising edge of the

internal clock, the internal high-side MOSFET turns on

until the PWM comparator trips. During this on time,

current ramps up through the inductor, sourcing cur-

rent to the output and storing energy in a magnetic

field. The current-mode feedback system regulates the

peak inductor current as a function of the output volt-

age error signal. Since the average inductor current is

nearly the same as the peak inductor current (assum-

ing that the inductor value is relatively high to minimize

ripple current), the circuit acts as a switch-mode

transconductance amplifier. It pushes the output LC filter

pole, normally found in a voltage-mode PWM, to a higher

frequency. To preserve inner loop stability and eliminate

inductor stair casing, a slope-compensation ramp is

summed into the main PWM comparator. During the

second half of the cycle, the internal high-side MOSFET

Dual, 180° Out-of-Phase, 1.4MHz, 750mA Step-

Down Regulator with POR and RSI/PFO

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11

NAME

PIN

MAX1970/MAX1972

MAX1971

FUNCTION

9

POR

POR

Active-Low Power-On Reset Output. Open-drain output goes high 16.6ms

(MAX1970) or 175ms (MAX1971 or MAX1972) after both outputs reach 92% of

nominal value, and RSI (MAX1971 only) is low.

10

EN

EN

Enable Input. Drive high to turn on both OUT1 and OUT2. Drive low to place the

device in shutdown.

PFO

—

Useful for detecting a valid USB input voltage.

11

—

RSI

Noninverting Reset Input. Causes POR to go low when RSI is high. Allows POR to

go high 175ms after RSI falls, if outputs are in regulation.

12

FBSEL2

FBSEL2

13

FBSEL1

FBSEL1

14

IN

IN

Power-Supply Voltage. Input range from 2.6V to 5.5V. Bypass with 10µF capacitor

to PGND.

15

LX2

LX2

Inductor Connection 2. Connect an inductor between LX2 and OUT2.

16

PGND

PGND

Power Ground

Pin Description (continued)