IR3531 datasheet(5/39 Pages) IRF

5 / 39 page

4+1 Phase Dual Output Control IC

IR3531

March 22, 2012 | FINAL | V2.27

PIN DESCRIPTIONS

PIN #

PIN NAME

PIN DESCRIPTION

Enable input. Grounding this pin shuts down the voltage regulators. Do not float this pin as the

logic state will be undefined.

VRHOT#

Open collector output of the VRHOT# comparator which drives low if Rail0 temperature exceeds

the programmed threshold. Connect external pull-up to bias.

VDRRY1

Open collector output that drives low during startup and under any external fault condition for

Rail1 regulator. Connect external pull-up to bias.

VDRRY

Open collector output that drives low during startup and under any external fault condition for

Rail0 regulator. Connect external pull-up to bias.

VCC

Bias buck regulator output, feedback pin, and bias input for internal circuitry.

Switching node for bias buck regulator.

V12V

Power Supply input supply rail.

ALERT#

Output pin for SVID Alert# interrupt. Open collector output that drives low to notify the master.

VCLK

SVID Clock Input. Clock is a high impedance input pin. It is driven by the open collector output of a

microprocessor and requires a pull-up resistor.

VDIO

SVID Data Input/Output. High impedance input when address, command or data bits are shifted in,

open drain output when acknowledging or sending data back to the microprocessor. Pin requires a

pull up resistor.

PHSSHED

Analog signal that represents the number of phases to be disabled. 0% to 25% VCC, no phases

disabled. 25% to 50% VCC, disable 1 phase. 50% to 75% VCC, disable 2 phases. 75% to 100% VCC,

disable 3 phases (if available).

IMON_R1

Voltage at this pin is proportional to Rail1 load current. It is also the input to the ADC for output

current register.

IMON

Voltage at this pin is proportional to Rail0 load current. It is also the input to the ADC for output

current register.

VDAC

Voltage Regulator Rail 0 reference voltage programmed by SVID. VDAC is also used as the A/D

reference during power up for pins ADDR/PSN, TSENS and ICCP.

Node for DCR thermal compensation network.

VDRP

Buffered, scaled and thermally compensated current signal for Rail0. Connect an external resistor

to FB to program converter output impedance.

Output of the error amplifier for Rail0.

PSC

Node for Power Savings mode compensation input.

Inverting input to the Error Amplifier for Rail0.

Remote sense amplifier output for Rail0.

VOSEN+

Rail0 remote sense amplifier input. Connect to output at the load.

VOSEN-

Rail0 remote sense amplifier input. Connect to ground at the load.

23, 24, 37, 38

IIN1-4

Current signals from the driver IC-s of Rail0.

TRACK

External tracking reference for Rail0.

BBR#

Body-braking

TM bus for Rail0 driver ICs to disable synchronous switches.

27, 28,

34, 35

PWM1-4

PWM outputs for Rail0. Each output is connected to the input of the driver IC. Connecting the

PWMx output to LGND disables the phase, allowing the IR3531 to operate as a 1, 2, 3, or 4 phase

controller.

SCLK

Synchronization clock input. Program ROSC using ROSC vs. Frequency to match the SCLK frequency.

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