IR3531 datasheet(17/39 Pages) IRF

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4+1 Phase Dual Output Control IC

IR3531

March 22, 2012 | FINAL | V2.27

Figure 7: TRACK Operation without Pre-Bias

The TRACK inputs have a typical 36mV offset from the

closed loop feedback operating point to ensure the error

amplifier is in an off state when TRACK=0V. Furthermore,

TRACK must exceed the respective VDAC by at least 100mV

to ensure VDAC has complete control of the Error Amplifier

as shown in Figures 6 and 7.

As a cautionary note the track input provides direct control

of the output PWM duty cycle. The presence of excessive

noise or glitches on TRACK when this input is active can

cause sudden increases in the PWM duty cycle (up to

100%), potentially causing damage to the power converter.

PWM CONTROL METHOD

The steady state control architecture utilized in the IR3531

is feed-forward voltage mode control with trailing edge

modulation. A high-gain wide-bandwidth voltage type

error amplifier is used to achieve accurate voltage

regulation and ultra-fast transient response. Feed-forward

control is established by varying the PWM ramp slope

proportionally to the input voltage resulting in the error

amplifier operating point being independent of the input

voltage. The input voltage can change due to variations in

the silver box output voltage or due to the wire and

PCB-trace voltage drop related to changes in load current.

All PWM ramp slopes are calibrated at initial power-up.

The PWM pulse is terminated once the PWM ramp

exceeds the Error Amplifier output voltage.

Under dynamic load transitions, the IR3531 utilizes our

patented Body Braking

TM algorithm allows all low-side

MOSFETs to be turned off during a load relaxation event

allowing the MOSFET body diodes to conduct and dissipate

some of the stored inductor energy and also speed up the

inductor current slew rate by introducing a larger voltage

across the inductor. Body Braking

TM reduces the peak

overshoot of the converter.

An error amplifier output voltage greater than the

common mode input range of the PWM comparator

results in 100% duty cycle regardless of the voltage of the

PWM ramp. The resulting PWM control loop is capable of

transitioning from 0% duty cycle to 100% duty cycle with

overlapping phases within a few tens of nanoseconds in

response to a load step decrease. Figure 8 on the next

page depicts PWM operating waveforms under various

conditions.

BODY BRAKING

In a conventional synchronous buck converter, the

minimum time required to reduce the current in the

inductor in response to a load-step decrease is:

MIN

MAX

SLEW

)

(





The slew rate of the inductor current can be significantly

increased by turning off the synchronous rectifier in

response to a load-step decrease. The switch node voltage

is then forced to decrease until conduction of the

synchronous rectifier’s body diode occurs. This increases

the voltage across the inductor from Vout to Vout +

VBODYDIODE. The minimum time required to reduce the

current in the inductor in response to a load transient

decrease is now:

BODYDIODE

MIN

MAX

SLEW







)

(

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