FT5000 datasheet(2/9 Pages) ETC2

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Singly-Terminated Bus Topology

Star Topology

Free Topology

= Terminatior

= FT device

Doubly-Terminated Bus Topology

Loop Topology

Figure 2: Free Topology Network

Configurations

The FT-X3 Communications Transformer

is a surface mount communications

transformer that’s compatible with

both the FT 5000 Smart Transceiver

and the previous-generation FT 3120/

FT 3150 Smart Transceivers. The FT-X3

Communications Transformer provides

equivalent noise

immunity to both the FT-X1 and FT-X2

Communication Transformers, the

previous-generation communication

transformers. However, the FT-X3

Communications Transformer is

not pin-compatible with the FT-X2

Communication Transformer (which

is also a surface mount transformer).

The FT 5000 Smart Transceiver can

also be used with the FT-X1 and FT-X2

Communication Transformers.

Backward Compatibility

The FT 5000 Smart Transceiver is fully

compliant with the TP/FT-10 channel

and can communicate with devices

that use Echelon’s FTT-10/FTT-10A

Transceivers, FT 3120/FT 3150 Smart

Transceivers, or LPT-10/LPT-11 Link Power

Transceivers.

The Neuron Core in the FT 5000 Smart

Transceiver uses the same instruction

set and architecture as the previous-

generation Neuron Core, with two new

additional instructions for hardware

multiplication and division. The Series

5000 Neuron Core is source code

compatible with applications written

for the Series 3100 Neuron Core.

Applications written for the Series

3100 Neuron Core must be recompiled

with the NodeBuilder® FX Development

Tool or the Mini FX Evaluation Kit before

they can be used with the FT 5000

Smart Transceiver.

The FT 5000 Smart Transceiver uses

Neuron firmware version 19. Firmware

versions prior to version 19 are not

compatible with the FT 5000 Smart

• Compliant with TP/FT-10 channels

using FT 3120®/FT 3150® Smart

Transceivers and FTT-10/FTT-10A/

LPT-10/LPT-11 Transceivers.

• 12 I/O pins with 35 programmable

standard I/O models.

• Supports up to 42KB of application

code space.

• 64KB RAM (44KB user-accessible)

and 16KB ROM on-chip memories.

• Unique 48-bit Neuron ID in every

device for network installation and

management.

• Very high common-mode noise

immunity.

• -40°C to +85°C operating tempera-

ture range.

Description

The FT 5000 Smart Transceiver includes

three independent 8-bit logical processors

to manage the physical MAC layer, the

network, and the user application. These

are called the Media-Access Control (MAC)

processor, the network (NET) processor,

and the application (APP) processor,

respectively (see Figure 1). At higher

system clock rates, there is also a fourth

processor to handle interrupts.

I / O

Comm

Port

External

Transformer

JTAG

Clock, Reset,

and Service

IRQ CPU

APP CPU

NET CPU

MAC CPU

Serial

Memory

Interface

NVM

(SPI or I2C)

ROM

(16K x 8)

RAM

(64K x 8)

2-6

Figure 1: FT 5000 Smart Transceiver Chip

The FT 5000 Smart Transceiver supports

polarity-insensitive cabling using a star,

bus, daisy-chain, loop, or combination

topology (see Figure 2). Thus, installers

don’t have to follow a strict set of wiring

rules imposed by other networking

technologies. Instead, they can install

wiring in the fastest and most cost-

effective manner, thereby saving time

and money. Free topology wiring also

simplifies network expansion by eliminating

restrictions on wire routing, splicing, and

device placement.

Transceiver. The Neuron firmware is

pre-programmed into the on-chip ROM.

The FT 5000 Smart Transceiver can also

be configured to read newer firmware

from external memories, allowing the

firmware to be upgraded over time.

Enhanced Performance

Faster system clock. The internal

system clock for the FT 5000 Smart

Transceiver can be user-configured to

run from 5MHz to 80MHz. The required

external crystal provides a 10MHz clock

frequency, and an internal PLL boosts

the frequency to a maximum of 80MHz

as the internal system clock speed. The

previous-generation Neuron 3120/3150

Core divided the external oscillator

frequency by two to create the internal

system clock. An FT 5000 Smart

Transceiver running with an 80MHz

internal system clock is thus 16 times

faster than a 10MHz Neuron 3120/3150

Core running.

The 5MHz internal system clock mode in

the FT 5000 Smart Transceiver provides

backward compatibility to support

timing-critical applications designed

for the 10MHz FT 3150 or FT 3120 Smart

Transceiver.

The Neuron Core inside the FT 5000

Smart Transceiver includes a built-

in hardware multiplier and divider to

increase the performance of arithmetic

operations.

Support for more network variables.

Because it uses Neuron firmware version

19, the FT 5000 Smart Transceiver

supports applications with up to 254

network variables and 127 aliases for

Neuron hosted devices (devices without

a host microprocessor). A Series 3100

Neuron Chip or Smart Transceiver with

Neuron firmware version 15 or earlier

supports up to 62 network variables and

62 aliases for Neuron hosted devices.

Series 3100 chips with Neuron firmware

version 16 or later support up to 254

network variables. You must use the

NodeBuilder FX Development Tool to

take advantage of 254 network variables.

Interrupts. The FT 5000 Smart

Transceiver lets developers define

application interrupts to handle

asynchronous events triggered by

selected state changes on any of

the 12 I/O pins, by on-chip hardware

timer-counter units, or by an on-chip

high-performance hardware system

timer. An application uses the Neuron C

interrupt() clause to define the interrupt

condition and the interrupt task that

handles the condition. The Neuron

C program runs the interrupt task

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