bus is 8 bits long and is always followed by an

acknowledge clock pulse.

The MAX5821 SDA and SCL drivers are open-drain out-

puts, requiring a pullup resistor to generate a logic high

voltage (see the Typical Operating Circuit ). Series

the input stages of the MAX5821 from high-voltage

spikes on the bus lines, and minimize crosstalk and

undershoot of the bus signals.

Bit Transfer

One data bit is transferred during each SCL clock

cycle. The data on SDA must remain stable during the

high period of the SCL clock pulse. Changes in SDA

while SCL is high are control signals (see the START

and STOP Conditions section). Both SDA and SCL idle

START and STOP Conditions

When the serial interface is inactive, SDA and SCL idle

high. A master device initiates communication by issu-

ing a START condition. A START condition is a high-to-

low transition on SDA with SCL high. A STOP condition

is a low-to-high transition on SDA, while SCL is high

(Figure 2). A START condition from the master signals

the beginning of a transmission to the MAX5821. The

master terminates transmission by issuing a not

acknowledge followed by a STOP condition (see

Acknowledge Bit (ACK)). The STOP condition frees the

bus. If a repeated START condition (Sr) is generated

instead of a STOP condition, the bus remains active.

When a STOP condition or incorrect address is detect-

ed, the MAX5821 internally disconnects SCL from the

serial interface until the next START condition, minimiz-

ing digital noise and feedthrough.

Early STOP Conditions

The MAX5821 recognizes a STOP condition at any

point during transmission except if a STOP condition

occurs in the same high pulse as a START condition

least one clock pulse must separate any START and

STOP conditions.

Repeated START Conditions

change of data direction on the bus. Such a change

occurs when a command word is required to initiate a

want to relinquish control of the bus. The MAX5821 seri-

al interface supports continuous write operations with or

change in direction of data flow.

Dual, 10-Bit, Low-Power, 2-Wire, Serial

Voltage-Output DAC

8

_______________________________________________________________________________________

POWER-DOWN

COMMAND BITS

PD1

PD0

MODE/FUNCTION

00

Power-up device. DAC output

restored to previous value.

01

Power-down mode 0. Power down

device with output floating.

10

Power-down mode 1. Power down

device with output terminated with

1k

Ω to GND.

11

Power-down mode 2. Power down

device with output terminated with

100k

Ω to GND.

Table 1. Power-Down Command Bits

SCL

SDA

STOP

CONDITION

START

CONDITION

REPEATED START CONDITION

START CONDITION

Figure 1. 2-Wire Serial Interface Timing Diagram