MAX5821 datasheet(3/13 Pages) MAXIM

3 / 13 page

Dual, 10-Bit, Low-Power, 2-Wire, Serial

Voltage-Output DAC

_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5k

Ω, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are

at VDD = +5V, TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input Hysteresis

0.05

VDD

Input Leakage Current

Digital inputs = 0 or VDD

±0.1

±1µA

Input Capacitance

6pF

DIGITAL OUTPUT (SDA)

Output Logic Low Voltage

VOL

ISINK = 3mA

0.4

Three-State Leakage Current

Digital inputs = 0 or VDD

±0.1

±1µA

Three-State Output Capacitance

6pF

DYNAMIC PERFORMANCE

Voltage-Output Slew Rate

0.5

V/µs

Voltage-Output Settling Time

To 1/2LSB code 100 hex to 300 hex or

300 hex to 100 hex (Note 5)

412

µs

Digital Feedthrough

Code = 000 hex, digital inputs from 0 to VDD

0.2

nV-s

Digital-to-Analog Glitch Impulse

Major carry transition (code = 1FF hex to 200

hex and 200 hex to 1FF hex)

nV-s

DAC-to-DAC Crosstalk

2.4

nV-s

POWER SUPPLIES

Supply Voltage Range

VDD

2.7

5.5

All digital inputs at 0 or VDD = 3.6V

115

205

Supply Current with No Load

IDD

All digital inputs at 0 or VDD = 5.5V

135

215

µA

Power-Down Supply Current

IDDPD

All digital inputs at 0 or VDD = 5.5V

0.3

µA

TIMING CHARACTERISTICS (FIGURE 1)

Serial Clock Frequency

fSCL

400

kHz

Bus Free Time Between STOP

and START Conditions

tBUF

1.3

µs

START Condition Hold Time

tHD,STA

0.6

µs

SCL Pulse Width Low

tLOW

1.3

µs

SCL Pulse Width High

tHIGH

0.6

µs

Repeated START Setup Time

tSU,STA

0.6

µs

Data Hold Time

tHD,DAT

0.9

µs

Data Setup Time

tSU,DAT

100

SDA and SCL Receiving

Rise Time

(Note 5)

300

SDA and SCL Receiving

Fall Time

(Note 5)

300

SDA Transmitting Fall Time

(Note 5)

20 +

0.1Cb

250

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