S1003 datasheet(16/42 Pages) SII

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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

S-1003 Series

Rev.1.0_00

Seiko Instruments Inc.

2. Manual reset function

The OUT pin voltage can be changed to detection status forcibly by the MR pin input voltage (VMR).

When not using the manual reset function, set VMR = VDD in the S-1003 Series xA type, and VMR = VSS in the

S-1003 Series xB type.

Caution Perform thorough evaluation in the actual application when using the MR pin in open. Due to the

parasitic capacitance of the MR pin, the manual reset function may malfunction when the power supply

fluctuates.

2. 1 S-1003 Series xA type (MR pin logic active "L")

(1) MR pin = "L"

When the VDD pin voltage is the release voltage (

+VDET) or more, the OUT pin changes to the detection status

from the release status immediately if a voltage of the MR pin input voltage "L" (VMRL) or less is applied to the

MR pin.

(2) MR pin = "H"

If a voltage of the MR pin input voltage "H" (VMRH) or more is applied to the MR pin, output from the OUT pin is

determined to be "H" or "L" depending on the VDD pin voltage.

After the passage of the delay time (tD), the OUT pin changes to the release status from the detection status.

VDD (

≥ +VDET)

VDD

VSS

MR pin input voltage "H" (VMRH)

Input from VDD pin

Input from MR pin

Output from OUT pin

MR pin input voltage "L" (VMRL)

(1)

(2)

Figure 18 Timing Chart of MR Pin Logic Active "L"

Remark

Since the MR pin is pulled up to the VDD pin internally, output from the OUT pin is determined to be "H" or "L" in

the floating status depending on the VDD pin voltage (Refer to Figure 19).

VSS

VDD

RMR

*1.

Parasitic diode

Figure 19

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