S1003 datasheet(17/42 Pages) SII

17 / 42 page

MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR

Rev.1.0_00

S-1003 Series

Seiko Instruments Inc.

2. 2 S-1003 Series xB type (MR pin logic active "H")

(1) MR pin = "H"

When the VDD pin voltage is the release voltage (

+VDET) or more, the OUT pin changes to the detection status

from the release status immediately if a voltage of the MR pin input voltage "H" (VMRH) or more is applied to the

MR pin.

(2) MR pin = "L"

If a voltage of the MR pin input voltage "L" (VMRL) or less is applied to the MR pin, output from the OUT pin is

determined to be "H" or "L" depending on the VDD pin voltage.

After the passage of the delay time (tD), the OUT pin changes to the release status from the detection status.

VDD (

≥ +VDET)

VDD

VSS

MR pin input voltage "H" (VMRH)

MR pin input voltage "L" (VMRL)

(1)

(2)

Input from VDD pin

Input from MR pin

Output from OUT pin

Figure 20 Timing Chart of MR Pin Logic Active "H"

Remark

Since the MR pin is pulled down to the VSS pin internally, output from the OUT pin is determined to be "H" or

"L" in the floating status depending on the VDD pin voltage (Refer to Figure 21).

VSS

VDD

RMR

*1.

Parasitic diode

Figure 21

S1003 Datasheet(PDF) 17 Page - Seiko Instruments Inc