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TSI352 Datasheet(PDF) 21 Page - Integrated Device Technology |
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TSI352 Datasheet(HTML) 21 Page - Integrated Device Technology |
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21 / 183 page ![]() 1. Functional Overview 21 Tsi352 User Manual 80D6000_MA001_03 Integrated Device Technology www.idt.com 1.4 Data Flow The following sections describe the data flow through the Tsi352 device. 1.4.1 Memory Read Transactions The conventional PCI memory read, memory read line, and memory read multiple commands are used to transfer memory read data. Tsi352 completes all memory read transactions as delayed transactions. Figure 3 shows the Tsi352 memory read flow. Figure 3: Memory Read Flow The following steps show the memory read flow through the Tsi352: • The read request from the initiator is posted/entered into the Non-Posted Queue • The transaction is terminated by signaling target retry to the initiator • When the target retry is received, the initiator is required to continue to repeat the same read transaction until at least one data transfer is completed or until a master/target abort is received • The Tsi352 then arbitrates for the destination bus and initiates a read transaction using the exact read address and read command — If the Tsi352 receives retry on the target bus, it continues to repeat the read transaction until at least one data transfer is completed, or until an error condition is encountered. • When the transaction is completed on the target bus, the Tsi352 transfers the data to the initiator when the initiator repeats the transaction When a memory read transaction targets non-prefetchable address space, the Tsi352 prefetches a single DWORD of data when the memory read command is used. For all other read transactions, the Tsi352 prefetches data according to the prefetch algorithm (see “Read Transactions” on page 30). PCI Slave PCI Master Non-posted Queue (4 entries) Non-posted Buffer Non-posted Buffer Non-posted Queue (4 entries) MUX Logic MUX Logic Delayed read request Delayed completion on the originating bus Request on the desitination bus on behalf of the originating bus request Read data buffered in the non-posted buffer (delayed read completion with target) |
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