TSI352 datasheet(41/183 Pages) IDT

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2. PCI Interface

Tsi352 User Manual

80D6000_MA001_03

Integrated Device Technology

www.idt.com

2.4.1.1

Master Latency Timer Expiration

If the Tsi352 is delivering posted write data when it terminates the transaction because the master

latency timer expires, it initiates another transaction to deliver the remaining write data. The address of

the transaction is updated to reflect the address of the current Dword to be delivered. If the Tsi352 is

prefetching read data when it terminates the transaction because the master latency timer expires, it

does not repeat the transaction to obtain more data.

2.4.2

Master Abort Received by Tsi352

If the Tsi352 initiates a transaction on the target bus and does not detect DEVSEL_b returned by the

target within five clock cycles of the Tsi352’s assertion of FRAME_b, the Tsi352 terminates the

transaction with a master abort. The Tsi352 sets the received master abort bit in the status register

corresponding to the target bus.

For delayed read and write transactions, when the master abort mode bit in the “Bridge Control

transactions, returns FFFF_FFFFh as data. When the master abort mode bit is 1, the Tsi352 returns

target abort on the initiator bus. The Tsi352 also sets the signaled target abort bit in the register

corresponding to the initiator bus.

When a master abort is received in response to a posted write transaction, the Tsi352 discards the

posted write data and makes no more attempts to deliver the data. The Tsi352 sets the received master

abort bit in the status register when the master abort is received on the primary bus, or it sets the

received master abort bit in the secondary status register when the master abort is received on the

secondary interface.

When a master abort is detected in response to a posted write transaction, and the master abort mode bit

is set, the Tsi352 also asserts P_SERR_b. The functionality must be enabled by the SERR_b enable bit

in the command register and not be disabled by the device-specific P_SERR_b disable bit for master

abort during posted write transactions (that is, master abort mode = 1; SERR_b enable bit = 1; and

P_SERR_b disable bit for master aborts = 0.)

2.4.3

Target Termination Received by Tsi352

When the Tsi352 initiates a transaction on the target bus and the target responds with DEVSEL_b, the

target can end the transaction with one of the following types of termination:

•

Normal termination (upon deassertion of FRAME_b)

•

Target retry

•

Target disconnect

•

Target abort

The Tsi352 handles these terminations in different ways, depending on the type of transaction being

performed.

When the Tsi352 performs a Type 1 to special cycle translation, a master abort is the expected

termination for the special cycle on the target bus. In this case, the master abort received bit is

not set, and the Type 1 configuration transaction is disconnected after the first data phase.

TSI352 Datasheet(PDF) 41 Page - Integrated Device Technology

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