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TSI352 Datasheet(PDF) 39 Page - Integrated Device Technology |
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TSI352 Datasheet(HTML) 39 Page - Integrated Device Technology |
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39 / 183 page  2. PCI Interface 39 Tsi352 User Manual 80D6000_MA001_03 Integrated Device Technology www.idt.com • The function number in address bits AD[10:8] is equal to 111b. • The bus command is a configuration write transaction. 2.3.4 Special Cycles The Type 1 configuration mechanism is used to generate special cycle transactions in hierarchical PCI systems. Special cycle transactions are ignored by a PCI-to-PCI bridge acting as a target and are not forwarded across the bridge. Special cycle transactions can be generated from Type 1 configuration write transactions in either the upstream or the downstream direction. The Tsi352 initiates a special cycle on the target bus when a Type 1 configuration write transaction is detected on the initiating bus and the following conditions are met during the address phase: • The lower two address bits on AD[1:0] are equal to 01b • The device number in address bits AD[15:11] is equal to 11111b • The function number in address bits AD[10:8] is equal to 111b. • The register number in address bits AD[7:2] is equal to 000000b • The bus number is equal to the value in the secondary bus number register in configuration space for downstream forwarding or equal to the value in the primary bus number register in configuration space for upstream forwarding • The bus command on C/BE_b is a configuration write command When the Tsi352 initiates the transaction on the target interface, the bus command is changed from a configuration write to a special cycle and the following actions occur: • The address and data are forwarded unchanged • Devices that use special cycles ignore the address and decode only the bus command • The data phase contains the special cycle message • The transaction is forwarded as a delayed transaction, but in this case the target response is not forwarded back (because special cycles result in a master abort) • Once the transaction is completed on the target bus, through detection of the master abort condition, Tsi352 responds with TRDY_b to the next attempt of the configuration transaction from the initiator. • If more than one data transfer is requested, the Tsi352 responds with a target disconnect operation during the first data phase. Tsi352 forwards Type 1-to-Type 1 configuration write transactions as delayed transactions. Type 1-to-Type 1 configuration write transactions are limited to a single data transfer. |
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