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TSI352 Datasheet(PDF) 34 Page - Integrated Device Technology

Part # TSI352
Description  This chapter discusses the following topics about the Tsi352
PDF  183 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

TSI352 Datasheet(HTML) 34 Page - Integrated Device Technology

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2. PCI Interface
34
Tsi352 User Manual
80D6000_MA001_03
Integrated Device Technology
www.idt.com
When the master repeats the transaction and starts transferring prefetchable read data from Tsi352 data
buffers while the read transaction on the target bus is still in progress and before a read boundary is
reached on the target bus, the read transaction starts operating in flow-through mode. Because data is
flowing through the data buffers from the target to the initiator, long read bursts can then be sustained.
In this case, the read transaction is allowed to continue until the initiator terminates the transaction, or
until an aligned 4-KB address boundary is reached, or until the buffer fills, whichever comes first.
When the buffer empties, Tsi352 indicates the stalled condition to the initiator by deasserting TRDY_b
until more read data is available; otherwise, Tsi352 does not insert any target wait states. When the
initiator terminates the transaction, the deassertion of FRAME_b on the initiator bus is forwarded to
the target bus. Any remaining read data is discarded.
Tsi352 uses a discard timer that starts counting when the delayed read completion is at the head of the
delayed transaction queue, and the read data is at the head of the read data queue. The initial value of
this timer can be set to one of two values, selectable through both the primary and secondary master
timeout value bits in the bridge control register. If the initiator does not repeat the read transaction
before the discard timer expires Tsi352 discards the read transaction and the read data from its queues.
Tsi352 also conditionally asserts P_SERR_b.
Tsi352 has the capability to post multiple delayed read requests, up to a maximum of three in each
direction. If an initiator starts a read transaction that matches the address and read command of a read
transaction that is already queued, the current read command is not posted as it is already contained in
the delayed transaction queue.



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