TSI352 datasheet(51/183 Pages) IDT

51 / 183 page

Tsi352 User Manual

80D6000_MA001_03

Integrated Device Technology

www.idt.com

Address Decoding

This chapter discusses the following:

•

“Overview of Address Decoding” on page 51

•

“Address Ranges” on page 51

•

“Address Forwarding” on page 51

•

“Memory Address Decoding” on page 55

•

“VGA Support” on page 59

3.1

Overview of Address Decoding

The Tsi352 uses three address ranges that control I/O and memory transaction forwarding. These

address ranges are defined by base and limit address registers in the Tsi352 configuration space. This

chapter describes these address ranges, as well as ISA-mode and VGA-addressing support.

3.2

Address Ranges

The Tsi352 uses the following address ranges that determine which I/O and memory transactions are

forwarded from the primary PCI bus to the secondary PCI bus, and from the secondary PCI bus to the

primary PCI bus:

•

One 32-bit I/O address range

•

One 32-bit memory-mapped I/O (non-prefetchable memory)

•

One 64-bit prefetchable memory address range

Transactions falling within these ranges are forwarded downstream from the primary PCI bus to the

secondary PCI bus. Transactions falling outside these ranges are forwarded upstream from the

secondary PCI bus to the primary PCI bus.

The Tsi352 uses a flat address space; that is, it does not perform any address translations. The address

space has no gaps — addresses that are not marked for downstream forwarding are always forwarded

upstream.

3.3

Address Forwarding

Tsi352 uses the following mechanisms that are defined in Tsi352 configuration space to specify the I/O

address space for downstream and upstream forwarding:

•

I/O base and limit address registers (“I/O Base Address Register—Offset 0x1C” on page 137)

•

The ISA enable bit (“Bridge Control Register—Offset 0x3C” on page 151)

•

The legacy ISA I/O enable bit (“Miscellaneous Control Register — Offset 0x58” on page 161)

TSI352 Datasheet(PDF) 51 Page - Integrated Device Technology

TSI352 Datasheet(HTML) 51 Page - Integrated Device Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL