AMC7823IRTAT datasheet(27/55 Pages) TI

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Yes

(2)

[ADR]+1

Yes

(3)

Direct-Mode

ADCinidle

Waitingnewtrigger

Auto-Mode,

InternalTriggeronly

SetDAVFbit;

Auto-Mode

(4)

Update ADC-n

DataRegister

Yes

NewADCConversionTrigger

ClearDAVFbitinAMC

Status/ConfigurationRegister

ClearallALR- inALRRegister

Set[ADR]=[SA]

(1)

Sample

Convert

Update ADC- TMPRY

Firstfourchannels?

Out-of-range?

[ADR]>[EA]?

(1)

Drive

PinLow

GALR

SetALR- BitinALRRegister

Apply2- sPulse(Low)

toPin

DAV

Drive

PinLow

DAV

AMC7823

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SLAS453F – APRIL 2005 – REVISED MARCH 2012

The bit GREF in the AMC Status/Configuration Register selects between two preset internal reference values.

When GREF = '0' (power-up default condition), the internal reference is set to 1.25V. When GREF = '1', the

internal reference is 2.5V. GREF must be cleared to '0' when the power supply is less than 5V.

When an external reference is applied, the input range is 0 to 2 × VREF, and is not affected by the bit GREF. In

this case, ideally SREF has been set to '1' and the internal reference is disconnected. This condition is preferred

for operating the AMC7823. If SREF = '0', the external reference overrides the internal reference, provided it can

accommodate a 10k

Ω load. To avoid input saturation, the external reference must not be greater than 2.5V when

the analog power supply is 5V, and must not be greater than 1.25V when the supply is 3V.

Figure 45 illustrates the ADC operation.

(1)

[SA] represents the first input channel, [EA] represents the last input channel. [ADR] represents the current input

channel. [SA3:SA0] is the address of [SA]. [EA3:EA0] is the address of [EA].

(2)

GALR pin goes high and bits ALR-n are cleared after new ADC Conversion trigger.

(3)

After reading the ADC Data Register, bit DAVF is cleared, and the DAV pin goes high.

(4)

In Auto-mode, bit DAVF is always cleared.

Figure 45. ADC Operation Flow Chart

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