AM4376 datasheet(149/261 Pages) TI

149 / 261 page

AM4376, AM4377, AM4378, AM4379

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SPRS851B – JUNE 2014 – REVISED APRIL 2015

5.12.8 External Memory Interfaces

The device includes the following external memory interfaces:

•

General-purpose memory controller (GPMC)

•

LPDDR2, DDR3, and DDR3L Memory Interface (EMIF)

5.12.8.1 General-Purpose Memory Controller (GPMC)

NOTE

For more information, see the Memory Subsystem and General-Purpose Memory Controller section

of the AM437x Sitara Processors Technical Reference Manual (SPRUHL7).

The GPMC is the unified memory controller used to interface external memory devices such as:

•

Asynchronous SRAM-like memories and ASIC devices

•

Asynchronous page mode and synchronous burst NOR flash

•

NAND flash

5.12.8.1.1 GPMC and NOR Flash—Synchronous Mode

Table 5-39 and Table 5-40 assume testing over the recommended operating conditions and electrical

characteristic conditions below (see Figure 5-33 through Figure 5-37).

Table 5-38. GPMC and NOR Flash Timing Conditions—Synchronous Mode

TIMING CONDITION PARAMETER

MIN

TYP

MAX

UNIT

Input Conditions

Input signal rise time

0.3

1.8

Input signal fall time

0.3

1.8

Output Condition

CLOAD

Output load capacitance

Table 5-39. GPMC and NOR Flash Timing Requirements—Synchronous Mode

OPP100

OPP50

NO.

UNIT

MIN

MAX

MIN

MAX

F12

tsu(dV-clkH)

Setup time, input data gpmc_ad[15:0] valid before output clock

3.5

13.2

gpmc_clk high

F13

th(clkH-dV)

Hold time, input data gpmc_ad[15:0] valid after output clock

2.5

2.75

gpmc_clk high

F21

tsu(waitV-clkH)

Setup time, input wait gpmc_wait[x](1) valid before output clock

3.5

13.2

gpmc_clk high

F22

th(clkH-waitV)

Hold time, input wait gpmc_wait[x](1) valid after output clock

2.5

gpmc_clk high

(1) In gpmc_wait[x], x is equal to 0 or 1.

Specifications

149

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