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AM4376 Datasheet(PDF) 148 Page - Texas Instruments |
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AM4376 Datasheet(HTML) 148 Page - Texas Instruments |
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148 / 261 page  RGMII[x]_TCLK (A) RGMII[x]_TD[3:0] (B) RGMII[x]_TCTL (B) 1 1st Half-byte TXERR TXEN 2nd Half-byte 1 2 RGMII[x]_TCLK 4 4 2 3 1 AM4376, AM4377, AM4378, AM4379 SPRS851B – JUNE 2014 – REVISED APRIL 2015 www.ti.com Table 5-36. Switching Characteristics for RGMII[x]_TCLK - RGMII Mode (see Figure 5-31) 10 Mbps 100 Mbps 1000 Mbps NO. PARAMETER UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX 1 tc(TXC) Cycle time, TXC 360 440 36 44 7.2 8.8 ns Pulse duration, TXC 2 tw(TXCH) 160 240 16 24 3.6 4.4 ns high 3 tw(TXCL) Pulse duration, TXC low 160 240 16 24 3.6 4.4 ns 4 tt(TXC) Transition time, TXC 0.75 0.75 0.75 ns Figure 5-31. RGMII[x]_TCLK Timing - RGMII Mode Table 5-37. Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode (see Figure 5-32) 10 Mbps 100 Mbps 1000 Mbps NO. PARAMETER UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX tsk(TD-TXC) TD to TXC output skew -0.5 0.5 -0.5 0.5 -0.5 0.5 1 ns tsk(TX_CTL-TXC) TX_CTL to TXC output skew -0.5 0.5 -0.5 0.5 -0.5 0.5 tt(TD) Transition time, TD 0.75 0.75 0.75 2 ns tt(TX_CTL) Transition time, TX_CTL 0.75 0.75 0.75 A. The Ethernet MAC and switch implemented in the device supports internal TX delay mode. B. Data and control information is transmitted using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the rising edge of RGMII[x]_TCLK and data bits 7-4 on the falling edge of RGMII[x]_TCLK. Similarly, RGMII[x]_TCTL carries TXEN on rising edge of RGMII[x]_TCLK and TXERR of falling edge of RGMII[x]_TCLK. Figure 5-32. RGMII[x]_TD[3:0], RGMII[x]_TCTL Timing - RGMII Mode 148 Specifications Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4376 AM4377 AM4378 AM4379 |
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