AM4376 datasheet(159/261 Pages) TI

159 / 261 page

AM4376, AM4377, AM4378, AM4379

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SPRS851B – JUNE 2014 – REVISED APRIL 2015

Table 5-43. GPMC and NOR Flash Timing Requirements—Asynchronous Mode

NO.

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

FA5(1)

tacc(d)

Data access time

H(5)

FA20(2)

tacc1-pgmode(d)

Page mode successive data access time

P(4)

FA21(3)

tacc2-pgmode(d)

Page mode first data access time

H(5)

(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional

clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock

edge. FA5 value must be stored inside the AccessTime register bit field.

(2) The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of

GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock

edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.

(3) The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by

active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.

(4) P = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK(6)

(5) H = AccessTime * (TimeParaGranularity + 1) * GPMC_FCLK(6)

(6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

Table 5-44. GPMC and NOR Flash Switching Characteristics—Asynchronous Mode

OPP100

OPP50

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

tR(d)

Rise time, output data gpmc_ad[15:0]

tF(d)

Fall time, output data gpmc_ad[15:0]

FA0

tw(be[x]nV)

Pulse duration, output lower-byte

Read

N(12)

enable and command latch enable

Write

N(12)

gpmc_be0n_cle, output upper-byte

enable gpmc_be1n valid time

FA1

tw(csnV)

Pulse duration, output chip select

Read

A(1)

gpmc_csn[x](13) low

Write

A(1)

FA3

td(csnV-advnIV)

Delay time, output chip select

Read

B(2) - 0.2

B(2) + 2.0

B(2) - 0.2

B(2) + 2.0

gpmc_csn[x](13) valid to output

Write

B(2) - 0.2

B(2) + 2.0

B(2) - 0.2

B(2) + 2.0

address valid and address latch

enable gpmc_advn_ale invalid

FA4

td(csnV-oenIV)

Delay time, output chip select gpmc_csn[x](13)

C(3) - 0.2

C(3) + 2.0

C(3) - 0.2

C(3) + 2.0

valid to output enable gpmc_oen invalid (Single

read)

FA9

td(aV-csnV)

Delay time, output address gpmc_a[27:1] valid

J(9) - 0.2

J(9) + 2.0

J(9) - 0.2

J(9) + 2.0

to output chip select gpmc_csn[x](13) valid

FA10

td(be[x]nV-csnV)

Delay time, output lower-byte enable and

J(9) - 0.2

J(9) + 2.0

J(9) - 0.2

J(9) + 2.0

command latch enable gpmc_be0n_cle, output

upper-byte enable gpmc_be1n valid to output

chip select gpmc_csn[x](13) valid

FA12

td(csnV-advnV)

Delay time, output chip select gpmc_csn[x](13)

K(10) - 0.2

K(10) + 2.0

K(10) - 0.2

K(10) + 2.0

valid to output address valid and address latch

enable gpmc_advn_ale valid

FA13

td(csnV-oenV)

Delay time, output chip select gpmc_csn[x](13)

L(11) - 0.2

L(11) + 2.0

L (11) - 0.2

L(11) + 2.0

valid to output enable gpmc_oen valid

FA16

tw(aIV)

Pulse durationm output address gpmc_a[26:1]

G(7)

invalid between 2 successive read and write

accesses

FA18

td(csnV-oenIV)

Delay time, output chip select gpmc_csn[x](13)

I(8) - 0.2

I(8) + 2.0

I(8) - 0.2

I(8) + 2.0

valid to output enable gpmc_oen invalid (Burst

read)

FA20

tw(aV)

Pulse duration, output address gpmc_a[27:1]

D(4)

valid - 2nd, 3rd, and 4th accesses

FA25

td(csnV-wenV)

Delay time, output chip select gpmc_csn[x](13)

E(5) - 0.2

E(5) + 2.0

E(5) - 0.2

E(5) + 2.0

valid to output write enable gpmc_wen valid

Specifications

159

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