AM4376 datasheet(186/261 Pages) TI

186 / 261 page

Device

Address and Control

Output Buffer

DDR Address and Control Input Buffers

Vtt

Address and Control

Terminator

Rtt

Device

Differential Clock

Output Buffer

DDR Differential CK Input Buffers

Routed as Differential Pair

Rcp

Clock Parallel

Terminator

Rcp

Cac

VDDS_DDR

0.1 µF

–

+ –

AM4376, AM4377, AM4378, AM4379

SPRS851B – JUNE 2014 – REVISED APRIL 2015

www.ti.com

5.12.8.2.1.4.4 Using Four 8-Bit DDR3 Devices

Two DDR3 devices are supported on the DDR3 interface consisting of four x8 DDR3 devices arranged as one

32-bit bank. These four devices may be mounted on one side of the PCB, or may be mirrored in pairs to save

board space at a cost of increased routing complexity and parts on the backside of the PCB.

5.12.8.2.1.4.5 CK and ADDR_CTRL Topologies, Four DDR3 Devices

Figure 5-62 shows the topology of the CK net classes and Figure 5-63 shows the topology for the corresponding

ADDR_CTRL net classes.

NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification.

Figure 5-62. CK Topology for Four DDR3 Devices

NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification.

Figure 5-63. ADDR_CTRL Topology for Four DDR3 Devices

5.12.8.2.1.4.6 CK and ADDR_CTRL Routing, Four DDR3 Devices

Figure 5-64 shows the CK routing for four DDR3 devices placed on the same side of the PCB. Figure 5-65

shows the corresponding ADDR_CTRL routing.

186

Specifications

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Product Folder Links: AM4376 AM4377 AM4378 AM4379

AM4376 Datasheet(PDF) 186 Page - Texas Instruments

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