AM4376 datasheet(183/261 Pages) TI

183 / 261 page

Device

Address and Control

Output Buffer

DDR3 Address and Control Input Buffers

Vtt

Address and Control

Terminator

Rtt

Device

Differential Clock

Output Buffer

DDR3 Differential CK Input Buffers

Routed as Differential Pair

Rcp

Clock Parallel

Terminator

Rcp

Cac

VDDS_DDR

0.1 µF

–

+ –

AM4376, AM4377, AM4378, AM4379

www.ti.com

SPRS851B – JUNE 2014 – REVISED APRIL 2015

5.12.8.2.1.4 DDR3 CK and ADDR_CTRL Topologies and Routing Definition

The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew between

them. CK is a bit more complicated because it runs at a higher transition rate and is differential. The following

subsections show the topology and routing for various DDR3 configurations for CK and ADDR_CTRL. The

figures in the following subsections define the terms for the routing specification detailed in Table 5-59.

5.12.8.2.1.4.1 Using Two DDR3 Devices (x8 or x16)

Two DDR3 devices are supported on the DDR3 interface consisting of two x8 DDR3 devices arranged as one

16-bit bank or two x16 DDR3 devices arranged as one 32-bit bank. These two devices may be mounted on one

side of the PCB, or may be mirrored in a pair to save board space at a cost of increased routing complexity and

parts on the backside of the PCB.

5.12.8.2.1.4.2 CK and ADDR_CTRL Topologies, Two DDR3 Devices

Figure 5-56 shows the topology of the CK net classes and Figure 5-57 shows the topology for the corresponding

ADDR_CTRL net classes.

NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification.

Figure 5-56. CK Topology for Two DDR3 Devices

NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification.

Figure 5-57. ADDR_CTRL Topology for Two DDR3 Devices

Specifications

183

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AM4376 Datasheet(PDF) 183 Page - Texas Instruments

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