AM4376 datasheet(180/261 Pages) TI

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DDR3 Keepout Region

Encompasses Entire DDR3 Routing Area

DDR3 Controller

AM4376, AM4377, AM4378, AM4379

SPRS851B – JUNE 2014 – REVISED APRIL 2015

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5.12.8.2.1.3.5 DDR3 Keepout Region

The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout region is

defined for this purpose and is shown in Figure 5-55. This region should encompass all DDR3 circuitry and the

region size varies with component placement and DDR3 routing. Additional clearances required for the keepout

region are shown in Table 5-54. Non-DDR3 signals should not be routed on the same signal layer as DDR3

signals within the DDR3 keepout region. Non-DDR3 signals may be routed in the region provided they are routed

on layers separated from DDR3 signal layers by a ground layer. No breaks should be allowed in the reference

ground or VDDS_DDR power plane in this region. In addition, the VDDS_DDR power plane should cover the

entire keepout region.

Figure 5-55. DDR3 Keepout Region

5.12.8.2.1.3.6 DDR3 Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry. Table 5-55

contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only

covers the bypass needs of the DDR3 interface and DDR3 devices. Additional bulk bypass capacitance may be

needed for other circuitry.

Table 5-55. Bulk Bypass Capacitors(1)

NO.

PARAMETER

MIN

MAX

UNIT

VDDS_DDR bulk bypass capacitor count

Devices

VDDS_DDR bulk bypass total capacitance

μF

DDR3#1 bulk bypass capacitor count

Devices

DDR3#1 bulk bypass total capacitance

μF

DDR3#2 bulk bypass capacitor count(2)

Devices

DDR3#2 bulk bypass total capacitance(2)

μF

DDR3#3 bulk bypass capacitor count(3)

Devices

DDR3#3 bulk bypass total capacitance(3)

μF

DDR3#4bulk bypass capacitor count(3)

Devices

DDR3#4 bulk bypass total capacitance(3)

μF

(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high-

speed (HS) bypass capacitors and DDR3 signal routing.

(2) Only used when two DDR3 devices are used.

(3) Only used when four DDR3 devices are used.

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