AM4376 datasheet(178/261 Pages) TI

178 / 261 page

AM4376, AM4377, AM4378, AM4379

SPRS851B – JUNE 2014 – REVISED APRIL 2015

www.ti.com

5.12.8.2.1.3.2 Compatible JEDEC DDR3 Devices

Table 5-51 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.

Table 5-51. Compatible JEDEC DDR3 Devices (Per Interface)

NO.

PARAMETER

CONDITION

MIN

MAX

UNIT

tC(DDR_CK) and

JEDEC DDR3 device speed grade

DDR3-1600

tC(DDR_CKn) = 2.5ns

JEDEC DDR3 device bit width

x32

JEDEC DDR3 device count(1)

Devices

(1) For valid DDR3 device configurations and device counts, see Section 5.12.8.2.1.3.1, Figure 5-49, and Figure 5-51.

5.12.8.2.1.3.3 DDR3 PCB Stackup

The minimum stackup for routing the DDR3 interface is a four-layer stack up as shown in Table 5-52. Additional

layers may be added to the PCB stackup to accommodate other circuitry, enhance signal integrity and

electromagnetic interference performance, or to reduce the size of the PCB footprint.

Table 5-52. Minimum PCB Stackup(1)

LAYER

TYPE

DESCRIPTION

Signal

Top signal routing

Plane

Ground

Plane

Split Power Plane

Signal

Bottom signal routing

(1) All signals that have critical signal integrity requirements should be routed first on layer 1. It may not be possible to route all of these

signals on layer 1 which requires some to be routed on layer 4. When this is done, the signal routes on layer 4 should not cross splits in

the power plane.

Table 5-53. PCB Stackup Specifications(1)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

PCB routing and plane layers

Signal routing layers

Full ground reference layers under DDR3 routing region(2)

Full VDDS_DDR power reference layers under the DDR3 routing region(2)

Number of reference plane cuts allowed within DDR3 routing region(3)

Number of layers between DDR3 routing layer and reference plane(4)

PCB routing feature size

mils

PCB trace width, w

mils

PCB BGA escape via pad size(5)

mils

PCB BGA escape via hole size

mils

Single-ended impedance, Zo(6)

ohms

Impedance control(7)(8)

Zo-5

Zo+5

ohms

(1) For the DDR3 device BGA pad size, see the DDR3 device manufacturer documentation.

(2) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer

return current as the trace routes switch routing layers.

(3) No traces should cross reference plane cuts within the DDR3 routing region. High-speed signal traces crossing reference plane cuts

create large return current paths which can lead to excessive crosstalk and EMI radiation.

(4) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.

(5) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available

for power routing. An 18-mil pad is required for minimum layer count escape.

(6) Zo is the nominal singled-ended impedance selected for the PCB.

(7) This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen Zo

defined by the single-ended impedance parameter.

(8) Tighter impedance control is required to ensure flight time skew is minimal.

178

Specifications

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